Due to technology scaling, smaller devices and lower operating voltages, next generation circuits are highly susceptible to soft errors. Another important problem confronting silicon scaling is static power consumption. In this paper, we analyze the effect of increasing threshold voltage (widely used for reducing static power consumption) on the soft error rate (SER). We find that increasing threshold voltage improves SER of transmission gate based flip-flops, but can adversely affect the robustness of combinational logic due to the effect of higher threshold voltages on the attenuation of transient pulses. We also show that clever use of high V t can improve the robustness of 6T-SRAMs.

Introduction 4.2 A First Glance 4.3 Interconnect Parameters --- Capacitance, Resistance, and Inductance 4.3.1 Capacitance 4.3.2 Resistance 4.3.3 Inductance 4.4 Electrical Wire Models 4.4.1 The Ideal Wire 4.4.2 The Lumped Model 4.4.3 The Lumped RC model 4.4.4 The Distributed rc Line 4.4.5 The Transmission Line 4.5 SPICE Wire Models 4.5.1 Distributed rc Lines in SPICE 4.5.2 Transmission Line Models in SPICE 4.6 Perspective: A Look into the Future chapter4.fm Page 103 Monday, September 6, 1999 1:44 PM 104 THE WIRE Chapter 4 4.1Introduction Throughout most of the past history of integrated circuits, on-chip interconnect wires were considered to be second class citizens that had only to be considered in special cases or when performing high-precision analysis. With the introduction of deep-submicron semiconductor technologies, this picture is undergoing rapid changes. The parasitics effects introduced by the wires displ