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Verification of Arithmetic Circuits with Binary Moment Diagrams
 IN PROCEEDINGS OF THE 32ND ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 1995
"... Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model ..."
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Cited by 93 (10 self)
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Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model the functionality of data path circuits operating over wordlevel data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, wherecomponentmodulesare first shownto implement their wordlevel specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the wordlevel circuit specification. Multipliers with word sizes of up to 256 bits hav...
Boolean Expression Diagrams
, 1997
"... This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable proper ..."
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Cited by 46 (5 self)
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This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One is a generalized version of the BDD applyoperator while the other can exploit the structural information of the Boolean expression. This ability is demonstrated by verifying that two di erent circuit implementations of a 16bit multiplier implement the same Boolean function. Using BEDs, this veri cation problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. Generally, BEDs are useful in applications, for example tautology checking, where the endresult as a reduced ordered BDD is small.
Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams
 IEEE Transactions on Computer Aided Design
, 1999
"... The combinational logiclevel equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or b ..."
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Cited by 16 (3 self)
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The combinational logiclevel equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression Diagrams (BEDs) and two algorithms for transforming a BED into a Reduced Ordered Binary Decision Diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDDs (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to...
On the Size of Randomized OBDDs and ReadOnce Branching Programs for kStable Functions
 In Proc. of the 16th Ann. Symp. on Theoretical Aspects of Computer Science (STACS), LNCS 1563
, 1999
"... In this paper, a simple technique which unifies the known approaches for proving lower bound results on the size of deterministic, nondeterministic, and randomized OBDDs and kOBDDs is described. ..."
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Cited by 12 (9 self)
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In this paper, a simple technique which unifies the known approaches for proving lower bound results on the size of deterministic, nondeterministic, and randomized OBDDs and kOBDDs is described.
Complexity Theoretical Results for Randomized Branching Programs
, 1998
"... This work is settled in the area of complexity theory for restricted variants of branching programs. Today, branching programs can be considered one of the standard nonuniform models of computation. One reason for their popularity is that they allow to describe computations in an intuitively straigh ..."
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Cited by 9 (8 self)
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This work is settled in the area of complexity theory for restricted variants of branching programs. Today, branching programs can be considered one of the standard nonuniform models of computation. One reason for their popularity is that they allow to describe computations in an intuitively straightforward way and promise to be easier to analyze than the traditional models. In complexity theory, we are mainly interested in upper and lower bounds on the size of branching programs. Although proving superpolynomial lower bounds on the size of general branching programs still remains a challenging open problem, there has been considerable success in the study of lower bound techniques for various restricted variants, most notably perhaps readonce branching programs and OBDDs (ordered binary decision diagrams). Surprisingly, OBDDs have also turned out to be extremely useful in practical applications as a data structure for Boolean functions. So far, research has concentrated on determinis...
Equivalence Checking of Integer Multipliers
 In Proceedings of ASPDAC '2001
, 2001
"... In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut poin ..."
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Cited by 5 (1 self)
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In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut points and thus dramatically improve the backward substitution process, (2) a layeredbackward substitution algorithm to reduce the number of substitutions, and (3) Multiplicative Power Hybrid Decision Diagrams (*PHDDs) as our wordlevel representation rather than *BMD in Hamaguchi's approach. Experimental results show that our approach can efficiently check the equivalence of two integer multipliers. To verify the equivalence of a array multiplier versus a Wallace tree multiplier, our approach takes about 57 CPU seconds using 11 Mbytes, while Stanion's approach took 21027 seconds using 130 MBytes. We also show that the complexity of our approach is upper bounded by 31 , where is the word size, but our experimental results show that the complexity of our approach grows cubically lly .
A Survey of Techniques for Formal Verification of Combinational Circuits
, 1997
"... With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal ..."
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Cited by 5 (1 self)
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With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. In this paper we survey some stateoftheart techniques used to perform automatic verification of combinational circuits. We classify the current approaches for combinational verification into two categories: functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. We briefly describe some of the methods in both the categories and discuss their merits and drawbacks.
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
 ACM Transactions on Design Automation of Electronic Systems
"... We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based o ..."
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Cited by 5 (2 self)
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We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are wellsuited to reliability and error susceptibility calculations. A few simple composition rules based on connectivity can be used to recursively build larger PTMs (representing entire logic circuits) from smaller gate PTMs. PTMs for gates in series are combined using matrix multiplication, and PTMs for gates in parallel are combined using the tensor product operation. PTMs can accurately calculate joint output probabilities in the presence of reconvergent fanout and inseparable joint input distributions. To improve computational efficiency, we encode PTMs as algebraic decision diagrams (ADDs). We also develop equivalent ADD algorithms for newly defined matrix operations such as eliminate variables and eliminate redundant variables, which aid in the numerical computation of circuit PTMs. We use PTMs to evaluate circuit reliability and derive polynomial approximations for circuit error probabilities in terms of gate error probabilities. PTMs can also analyze the effects of logic and electrical masking on error mitigation. We show that ignoring logic masking can overestimate errors by an order of magnitude. We incorporate electrical masking by computing error attenuation probabilities, based on analytical models, into an extended PTM
Equivalence Checking of Hierarchical Combinational Circuits
, 1999
"... This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of the circuits to reuse results obtained from one part of the circuits in other parts. We demonstr ..."
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This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of the circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate the method on large adder and multiplier circuits.