Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction High-speed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In...

To enable floating-point (FP) signal processing applications in low-power mobile devices, we propose lightweight floating-point arithmetic. It offers a wider range of precision/power/speed/area tradeoffs, but is wrapped in forms that hide the complexity of the underlying implementations from both multimedia software designers and hardware designers. Libraries implemented in C and Verilog provide flexible and robust floating-point units with variable bit-width formats, multiple rounding modes and other features. This solution bridges the design gap between software and hardware, and accelerates the design cycle from algorithm to chip by avoiding the translation to fixed-point arithmetic. We demonstrate the effectiveness of the proposed scheme using the inverse discrete cosine transform (IDCT), in the context of video coding, as an example. Further, we implement lightweight floating-point IDCT into hardware and demonstrate the power and area reduction.

In this thesis we explore power dissipation of multiplier circuits. We analyze power trade-offs of both array multipliers and Wallace tree multipliers. Focusing an Wallace tree multipliers, we analyze the minimization of switching activity by latch insertion. The main contribution of this thesis is an adaptation of "inverse polarity optimization," a technique developed for delay optimization of adders. We use this to successfully reduce the incidence of false switching in Wallace tree multipliers through the removal of redundant inverters. Our results indicate that, using this technique, up to 25% power reduction can be achieved for minimum-sized multipliers.

On the Synthesis-Oriented characteristics of high performance, deep-submicron CMOS VLSI cell libraries. A method to evaluate the “synthesis-oriented ” quality of cell libraries, as well as their ability to be efficiently inferred and used during the technology mapping step of DesignCompiler is presented. The definition of both the functional variety of synthesis-oriented advanced cell libraries and the low power physical design methodology for HCMOS6 (0.35 µm minimum channel length) forms part of an investigatory phase, prior to the creation of an ultra-low power cell library based on HCMOS7 (0.25 µm minimum channel length) at low supply voltage. On the Synthesis-Oriented characteristics of high performance, deep-submicron CMOS VLSI cell libraries.