We describe a class of nonlinear circuits that accurately embody product-of-power-law relationships in the current signal domain. We call these circuits multiple-input translinear element (MITE) networks. A MITE is a circuit element that produces an output current that is exponenial in a weighted sum of its input voltages. We describe intuitively the basic operation of MITE networks and we show experimental data from a squaring-reciprocal circuit breadboarded from bipolar-- floating-gate MOS (biFGMOS) MITEs that we fabricated in a 2--m double-poly CMOS process available through MOSIS. 1. PRODUCT-OF-POWER-LAW CIRCUITS Products, quotients, and power-law relationships figure prominently in many signal and information processing algorithms. Consequently, analog circuits embodying such relaionships are important components in the construction of analog VLSI information processing systems. In the Nonlinear Circuits Handbook from Analog Devices, we find the following clear description of a ...

We discuss the possibility of developing high-quality floating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental proceedures to address this issue and find acceptable floating-gate circuit behavior with MOS capacitors. First, we simultaniously characterize a MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a finite, but usable range. Second, we characterize two typical floating-gate MOS circuit primatives, a floating-gate amplifier and a multiple-input translinear element, two basic circuits that rely heavily on the linearity of the capacitors that couple into the floating gates. Our measurements show that floating-gate circuits with MOS-capacitor control gates behave like their counterparts built with linear capacitors over specif...

Since the first reported floating-gate structure in 1967, floatinggate transistors have been used widely to store digital information for long periods in structures such as EPROMs and EEPROMs. Recently, floating-gate devices have found applications as analog memories, analog and digital circuit elements, and adaptive processing elements. Floating-gate devices have found commerical applications, e.g. ISD, for long-term non-volatile information storage devices for analog applications. The focus of floating-gate devices has been towards fabrication in standard CMOS processes, as opposed to the specialized processes for fabricating digital nonvolatile memories. Floating-gate circuits can be designed at any or all of three levels: analog memory elements, capacitive-based circuit elements, and adaptive circuit elements. In 1967, Kahng and Sze reported the first floating-gate structure as a mechanism for nonvolatile information storage [1]. Since then, floating-gate transistors have been use...

The exponential behavior of MOSFETs in subthreshold operation has recently been exploited to build CMOS translinear circuits such as multipliers and log-domain filters. A major obstacle in developing a practical CMOS implementation is the variation in threshold voltage between devices. In translinear circuits, these voltage offsets manifest themselves as gain errors in the current-mode outputs. We have designed a floating-gate CMOS current mirror that can adapt its gain to compensate for these errors. The adaptation process uses only hot-electron injection, so the high voltages typically associated with tunneling are not needed. A small array of these circuits were fabricated in a standard 1.2 ¯m double-poly CMOS process. We demonstrate gain adaptation and discuss the nonlinearity introduced by the adaptive mirror. 1. INTRODUCTION Translinear circuits use devices whose transconductance is linear with current (i.e., the current through the device is an exponential function of the input...

An improved analogue VLSI implementation of the inner hair cell is presented. The Meddis inner hair cell model is a widely accepted, computationally convenient computer model. We transfer this model into the current-domain and implement it using translinear and log-domain circuits. The function of the transformed model and circuit are tested against physiological data and the Meddis model. These tests include (a) rate intensity functions for onset and steady state response; (d) recovery of spontaneous activity; and (c) Low-frequency selectivity. Our circuit mimics the Meddis model in these tests, and is flexible enough to be `tuned' to behave in a similar way to the Meddis model and to the biological inner hair cell ii Acknowledgements I would like to express by gratitude to my supervisor, Dr Andr van Schaik for opening my eyes to, the mix of analogue VLSI design and physiology, the concept of `neuromorphic engineering' and for the assistance and guidance he provided me with throughout the semester. My thanks goes to all who have given support and proof read whole or part of this documents especially my girlfriend Alexandra Lobb for her interest and continuos enthusiasm. I also wish to extend thanks to Cheng Soon Ong for valuable comments, Paul Williams and Jenny Turtle at Endocrinology, My brother, Lachlan for his insights into determining the perfect sentence structure and my both my parents.

We describe two systematic procedures for synthesizing mutlipleinput translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each of these procedures with an example. 1. MITE NETWORKS: THE SYNTHESIS PROBLEM We recently introduced a class of translinear circuits, called multiple -input translinear element (MITE) networks, that accurately embody product-of-power-law relationships in the current signal domain [1--3]. The MITE is a circuit primitive that produces an output current that is exponential in a weighted sum of the MITE's input voltages [2, 4]. For a given produ...

We present the bump mixture model, a statistical model for analog data where the probabilistic semantics, inference, and learning rules derive from low-level transistor behavior. The bump mixture model relies on translinear circuits to perform probabilistic inference, and floating-gate devices to perform adaptation. This system is low power, asynchronous, and fully parallel, and supports various on-chip learning algorithms. In addition, the mixture model can perform several tasks such as probability estimation, vector quantization, classification, and clustering. We tested a fabricated system on clustering, quantization, and classification of handwritten digits and show performance comparable to the E-M algorithm on mixtures of Gaussians. 1

We define the multiple-input translinear element (MITE), a versatile circuit primitive from which we can construct lowvoltage translinear circuits and log-domain filters. A K-input MITE produces an output current that is exponential in a weighted sum of its K input voltages. We briefly discuss six MITE implementations and show experimental data from two of these six that we have fabricated in a 2--m double-poly CMOS process available through MOSIS. 1. TRANSLINEAR CIRCUIT ELEMENTS In 1975, Barrie Gilbert [1] coined the word translinear to describe a class of nonlinear circuits whose operation is based on the exponential current--voltage relationship of the bipolar transistor. The word translinear derives from a contraction of one way of expressing the exponential current--voltage relationship of the bipolar---that is, the bipolar's transconduc- tance is linear in the current flowing into its collector terminal. The subthreshold MOS transistor also has an exponential current--vo...