A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

In the next few years, logic capacities for field-programmable gate arrays are expected to exceed one million gates per device. While this expansion of FPGA device resources offers the promise of exceptional finegrained performance for developing technologies such as ASIC prototyping and FPGA computing, supporting computer-aided design tools have yet to be developed to target these devices rapidly and efficiently. This paper addresses the compilation time issue for routing array FPGAs with segmented routing architectures. By treating the routing problem as an A search, it is possible to trade additional device routing resources for decreased router run-time by converting an exhaustive breadth-first maze route into a shorter depth-first route. It is shown that for the depth-first case, the sparse nature of FPGA routing switches in commerical architectures, such as the Xilinx XC4000 family, necessitates an additional localized search near net inputs, called domain negotiation, to aid in d...

With recent advances in silicon device technology, a new branch of computer architecture, reconfigurable computing, has emerged. While this computing domain holds the promise of exceptional fine-grained parallel performance, the amount of time required to compile a program to a reconfigurable computing platform can be prohibitive for many applications.

Abstract—Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works. Index Terms—Physical design, routing, spanning tree, Steiner tree. I.

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation /verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

This report describes the problem of printed circuit board routing. An overview of circuit board construction is given. The algorithms in a printed circuit board router used for fully automatic routing of highdensity circuit boards are described. Running times of a few minutes have resulted from a new data structure for efficient representation of the routing grid, quick searches for optimal solutions, and generalizations of Lee's algorithm for maze routing. 1 1. Introduction Even though printed circuit board routing is a venerable problem in computer-aided design, fully automatic routing of densely packed boards remains an elusive goal. In current industry practice, a program is used to make most connections automatically. The remainder is left for manual completion. This procedure is a poor second to fully automatic routing. It leaves the possibility for introducing errors in the routing of the final connections. More seriously, it is an investment in time and effort that makes s...

Floorplanning is an essential design step for hierarchical, building-module design methodology. Floorplanning provides early feedback that evaluates architectural decisions, estimates chip areas, and estimates delay and congestion caused by wiring. As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and intellectual property (IP) modules are widely used. This trend makes floorplanning much more critical to the quality of a very large-scale integration (VLSI) design than ever. This chapter starts with the formulation of the floorplanning problem. After the problem formulation, the two most popular approaches to floorplanning, simulated annealing and analytical formulations, are discussed. On the basis of simulated annealing, three popular floorplan representations, normalized Polished expression, B*-tree, and sequence pair, are further covered and compared. Some modern floorplanning issues such as soft modules, fixed-outline constraints, and large-scale designs are also addressed.

(NRE) costs associated with the development of Integrated Circuits (ICs) is becoming extremely high. One of the main reasons is the high cost of preparing and processing IC fabrication masks. The design effort and cost can be reduced by employing Structured Application-Specific ICs (Structured ASICs). Structured ASICs are partially fabricated ICs that require only a subset of design-specific custom masks for their completion. In this dissertation, we investigate the impact of design-specific masks on the area, delay, power, and die-cost of Structured ASICs. We divide Structured ASICs into two categories depending on the types of masks (metal and/or via masks) needed for customization: Metal-Programmable Structured ASICs (MPSAs) that require custom metal and via masks; and Via-Programmable Structured ASICs (VPSAs) that only require custom via masks. We define the metal layers used for routing that can be configured by one or more via, or metal-and-via masks as configurable layers. We then investigate the area, delay, power, and cost trends for MPSAs and VPSAs as a function of configurable layers.