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190
Statistical Optimization of Leakage Power Considering Process Variations using DualVth and Sizing
, 2004
"... Increasing levels of process variability in sub100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware DualVt and sizing optimization that considers both the variability in performance and leakage of a design ..."
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Cited by 22 (3 self)
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Increasing levels of process variability in sub100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware DualVt and sizing optimization that considers both the variability in performance and leakage of a design. While extensive work has been performed in the past on statistical analysis methods, circuit optimization is still largely performed using deterministic methods. We show in this paper that deterministic optimization quickly looses effectiveness for stringent performance and leakage constraints in designs with significant variability. We then propose a statistically aware dualVt and sizing algorithm where both delay constraints and sensitivity computations are performed in a statistical manner. We demonstrate that using this statistically aware optimization, leakage power can be reduced by 1535 % compared to traditional deterministic analysis. The improvements increase for strict delay constraints making statistical optimization especially important for high performance designs.
Slope propagation in static timing analysis
 ICCAD2000: IEEE/ACM International Conference on Computer Aided Design
, 2000
"... Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may ..."
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Cited by 22 (2 self)
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Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit. Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay. Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit. We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods. We propose a new timing analysis algorithm which resolves both these issues. The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path. The algorithm for propagating the corresponding required times is also presented. We prove that the proposed algorithm identifies a circuit’s true critical path, where the traditional timing analysis method may not. We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit’s transistor and gate sizes. In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy. Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits. Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time. 2
UncertaintyAware Circuit Optimization
 IN DAC
, 2002
"... Almost by definition, welltuned digital circuits have a large number of equally critical paths, which form a socalled "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inac ..."
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Cited by 21 (1 self)
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Almost by definition, welltuned digital circuits have a large number of equally critical paths, which form a socalled "wall" in the slack histogram. However, by the time the design has been through manufacturing, many uncertainties cause these carefully aligned delays to spread out. Inaccuracies in parasitic predictions, clock slew, modeltohardware correlation, static timing assumptions and manufacturing variations all cause the performance to vary from prediction. Simple statistical principles tell us that the variation of the limiting slack is larger when the height of the wall is greater. Although the wall may be the optimum solution if the static timing predictions were perfect, in the presence of uncertainty in timing and manufacturing, it may no longer be the best choice. The application of formal mathematical optimization in transistor sizing increases the height of the wall, thus exacerbating the problem. There is also a practical matter that schematic restructuring downstream in the design methodology is easier to conceive when there are fewer equally critical paths. This paper describes a method that gives formal mathematical optimizers the incentive to avoid the wall of equally critical paths, while giving up as little as possible in nominal performance. Surprisingly, such a formulation reduces the degeneracy of the optimization problem and can render the optimizer more effective. This "uncertaintyaware" mode has been implemented and applied to several highperformance microprocessor macros. Numerical results are included.
A New Statistical Optimization Algorithm for Gate Sizing
"... In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a ..."
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Cited by 21 (2 self)
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In this paper, we approach the gate sizing problem in VLSI circuits in the context of increasing variability of process and circuit parameters as technology scales into the nanometer regime. We present a statistical sizing approach that takes into account randomness in gate delays by formulating a robust linear program that can be solved efficiently. We demonstrate the efficiency and computational tractability of the proposed algorithm on the various ISCAS’85 benchmark circuits. Across the benchmarks, compared to the deterministic approach, the power savings range from 23 − 30 % for the same timing target and the yield level, the average power saving being 28%. The runtime is reasonable, ranging from a few seconds to around 10 mins, and grows linearly.
Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits
 Proc. ACM/IEEE DAC
"... Gate oxide tunneling current (Igate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (Tox) goes below 15˚A. Increasing the value of Tox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be ..."
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Cited by 21 (0 self)
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Gate oxide tunneling current (Igate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (Tox) goes below 15˚A. Increasing the value of Tox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible Tox values to each transistor. In this paper, we propose an algorithm for dual Tox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low Tox, our approach achieves an average leakage reduction of 83 % under 100nm models.
Hybrid structured clock network construction
 Proceedings of the 2001 IEEE/ACM international conference on Computeraided design
, 2001
"... This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, us ..."
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Cited by 18 (0 self)
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This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a postprocessing step, wire width optimization under an accurate higherorder delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree. 1.
Power Minimization using Simultaneous Gate Sizing DualVdd and DualVth Assignment
 in Proceedings of the Design Automation Conference, 2004
"... We develop an approach to minimize total power in a dualVdd and dualVth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second phase proceeds in a forward topological fashio ..."
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Cited by 17 (1 self)
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We develop an approach to minimize total power in a dualVdd and dualVth design. The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second phase proceeds in a forward topological fashion and both sizes and reassigns gates to high Vdd to enable significant static power savings through high Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS and dualVth/sizing algorithms demonstrate the advantage of the algorithm over a range of activity factors, including an average power reduction of 30 % (50%) at high (nominal) primary input activities.
Network Delays and Link Capacities in ApplicationSpecific Wormhole NoCs
, 2007
"... Networkonchip (NoC) based applicationspecific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on and offchip interconnection ne ..."
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Cited by 17 (4 self)
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Networkonchip (NoC) based applicationspecific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on and offchip interconnection networks which employ uniformcapacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoCbased systems. The algorithm should minimize the communication resource costs under QualityofService timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.
Optimal Power Control in Interference Limited Fading Wireless Channels with Outage Probability Specifications
, 2000
"... We propose a new method of power control for interference limited wireless networks with Rayleigh fading of both the desired and interference signals. Our method explictly takes into account the statistical variation of both the received signal and interference power, and optimally allocates powe ..."
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Cited by 16 (2 self)
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We propose a new method of power control for interference limited wireless networks with Rayleigh fading of both the desired and interference signals. Our method explictly takes into account the statistical variation of both the received signal and interference power, and optimally allocates power subject to constraints on the probability of fading induced outage for each transmitter/receiver pair. We establish several results for this type of problem. For the case
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 16 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After