Results 1  10
of
191
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 109 (32 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
 IEEE Transactions on ComputerAided Design
, 1993
"... this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of ..."
Abstract

Cited by 107 (19 self)
 Add to MetaCart
(Show Context)
this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area
Interconnect design for deep submicron ICs
 IN PROC. INT. CONF. ON COMPUTER AIDED DESIGN
, 1997
"... Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we ..."
Abstract

Cited by 72 (22 self)
 Add to MetaCart
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of interconnect design as the technology feature size rapidly decreases towards below 0.1 micron. Then, we present commonly used interconnect models and a set of interconnect design and optimization techniques for improving interconnect performance and reliability. Finally, we present comparisons of different optimization techniques in terms of their efficiency and optimization results, and show the impact of these optimization techniques on interconnect performance in each technology generation from the 0.35µm to 0.07µm projected in the National Technology Roadmap for Semiconductors.
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
Abstract

Cited by 66 (10 self)
 Add to MetaCart
(Show Context)
We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints
 In DAC
, 2005
"... Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment ..."
Abstract

Cited by 43 (1 self)
 Add to MetaCart
(Show Context)
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics are treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold voltage assignment. An extremely fast runtime is achieved by casting the problem as a secondorder conic problem and solving it using efficient interiorpoint optimization methods. When compared to the deterministic optimization, the new algorithm, on average, reduces static power by 31 % and total power by 17 % without the loss of parametric yield. The run time on a variety of public and industrial benchmarks is 30X faster than other known statistical power minimization algorithms.
Optimal Wiresizing for Interconnects with Multiple Sources
 ACM Trans. on Design Automation of Electronics Systems
, 1996
"... this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading subtrees (LSTs), and show that the optimal wiresizing solution ..."
Abstract

Cited by 42 (18 self)
 Add to MetaCart
this paper, we study the optimal wiresizing problem for nets with multiple sources under the RC tree model and the Elmore delay model. We decompose the routing tree for a multisource net into the source subtree (SST) and a set of loading subtrees (LSTs), and show that the optimal wiresizing solution satisfies a number of interesting properties, including: the LST separability, the LST monotone property, the SST local monotone property, and the dominance property. Furthermore, we study the optimal wiresizing problem using a variable segmentdivision rather than an a priori fixed segmentdivision as in all previous works and reveal the bundled refinement property. These properties lead to efficient algorithms to compute the optimal solutions. We have tested our algorithm on nets extracted from the multilayer layout for a highperformance Intel microprocessor. Accurate SPICE simulation shows that our methods reduce the average delay by up to 23.5% and the maximum delay by up to 37.8%, respectively, for the submicron CMOS technology when compared to the minimal wire width solution. In addition, the algorithm based on the variable segmentdivision yields a speedup of over 1003 time and does not lose any accuracy, when compared with the algorithm based on the a priori fixed segmentdivision
Standby power minimization through simultaneous threshold voltage and circuit sizing
 Proc. DAC
, 1999
"... We present a new approach for estimation and optimization of the average standby power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of “dominant leakage states” and use state probabilities. Our meth ..."
Abstract

Cited by 36 (3 self)
 Add to MetaCart
(Show Context)
We present a new approach for estimation and optimization of the average standby power dissipation in large MOS digital circuits. To overcome the complexity of state dependence in average leakage estimation, we introduce the concept of “dominant leakage states” and use state probabilities. Our method achieves speedups of 3 to 4 orders of magnitude over exhaustive SPICE simulations while maintaining accuracies within 9 % of SPICE. This accurate estimation is used in a new sensitivitybased leakage and performance optimization approach for circuits using dual V t processes. In tests on a variety of industrial circuits, this approach was able to obtain 81100 % of the performance achievable with all low V t transistors, but with 1/3 to 1/6 the standby current.
LowPower FPGA Using Predefined DualVdd/DualVt Fabrics
 FPGA'04
, 2004
"... Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt ..."
Abstract

Cited by 34 (12 self)
 Add to MetaCart
(Show Context)
Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including powersensitivity based voltage assignment and simulatedannealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the predefined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the predesigned dualVdd layout pattern introduces nonnegligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dualVdd FPGAs. To our best knowledge, it is the first indepth study on applying both dualVdd and dualVt to FPGA considering circuits, fabrics and CAD algorithms.
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
Abstract

Cited by 34 (1 self)
 Add to MetaCart
(Show Context)
Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.