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212
A Complementary Pair of FourTerminal Silicon Synapses
 Analog Integrated Circuits and Signal Processing
, 1997
"... We have developed a complementary pair of pFET and nFET floatinggate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hotelectron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory ..."
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Cited by 12 (8 self)
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We have developed a complementary pair of pFET and nFET floatinggate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hotelectron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memoryupdate rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated at subthres...
A Comprehensive CircuitLevel Model of VerticalCavity SurfaceEmitting Lasers
 IEEE Journal of Lightwave Technology
, 1999
"... The increasing interest in verticalcavity surfaceemitting lasers (VCSEL's) requires the corresponding development of circuitlevel VCSEL models for use in the design and simulation of optoelectronic applications. Unfortunately, existing models lack either the computational efficiency or the compreh ..."
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Cited by 9 (0 self)
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The increasing interest in verticalcavity surfaceemitting lasers (VCSEL's) requires the corresponding development of circuitlevel VCSEL models for use in the design and simulation of optoelectronic applications. Unfortunately, existing models lack either the computational efficiency or the comprehensiveness warranted by circuitlevel simulation. Thus, in this paper we present a comprehensive circuitlevel model that accounts for the thermal and spatial dependence of a VCSEL's behavior. The model is based on multimode rate equations and empirical expressions for the thermal dependence of the activelayer gain and carrier leakage, thereby facilitating the simulation of VCSEL's in the context of an optoelectronic system. To confirm that our model is valid, we present sample simulations that demonstrate its ability to replicate typical dc, smallsignal, and transient operation, including temperaturedependent lightcurrent (LI) curves and modulation responses, multimode behavior, and diffusive turnoff transients. Furthermore, we verify our model against experimental data from four devices reported in the literature. As the results will show, we obtained excellent agreement between simulation and experiment. Index TermsCircuitlevel models, multimode rate equations, spatial hole burning, thermal modeling, verticalcavity surfaceemitting lasers (VCSEL's). I.
LowPower CMOS Library Design Methodology
, 1994
"... The emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The goal of this project is to develop a methodology for designing low power circuits and cells, and to implement this methodology in constructing a general purpose cell libr ..."
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Cited by 8 (0 self)
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The emphasis in VLSI design has shifted from high speed to low power due to the proliferation of portable electronic systems. The goal of this project is to develop a methodology for designing low power circuits and cells, and to implement this methodology in constructing a general purpose cell library that can be used to design low power integrated circuits. The design methodology encompasses all aspects of circuit design; it optimizes transistor size, logic style, layout style, cell topology, and circuit design for low power operation. The cell library is implemented within the framework of the LagerIV CAD suite for rapid logic synthesis and layout generation. Several chips designed with the low power library demonstrate the power reduction that can be achieved. The entire cell library is characterized to determine typical delay, average power consumption, and area for each cell so the IC designer can make reasonable speed, area, and power estimations while still in the architecture design stage. Acknowledgements First, I would like to thank my research advisor Professor Bob Broderson for his support and guidance of this research. And most importantly, it is because of him and a few others that I am at
A multigrid preconditioner for the semiconductor equations
 SIAM J. Sci. Comput
, 1996
"... Abstract. Amultigrid preconditioned conjugate gradient algorithm is introduced into a semiconductor device modeling code, DANCIR. This code simulates a wide variety of semiconductor devices bynumerically solving the driftdi usion equations. The most time consuming aspect of the simulation is the so ..."
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Cited by 7 (0 self)
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Abstract. Amultigrid preconditioned conjugate gradient algorithm is introduced into a semiconductor device modeling code, DANCIR. This code simulates a wide variety of semiconductor devices bynumerically solving the driftdi usion equations. The most time consuming aspect of the simulation is the solution of three linear systems within each iteration of the Gummel method. The original version of DANCIR uses a conjugate gradient iteration preconditioned by an incomplete Cholesky factorization. In this paper, we consider the replacement of the Cholesky preconditioner by amultigrid preconditioner. To adapt the multigrid method to the driftdi usion equations, interpolation, projection, and coarse grid discretization operators need to be developed. These operators must take into account anumber of physical aspects that are present intypical devices: wide scale variation in the partial di erential equation (PDE) coe cients, small scale phenomena suchascontact points, and an oxide layer. Additionally, suitable relaxation procedures must be designed that give good smoothing numbers in the presence of anisotropic behavior. The resulting method is compared with the Cholesky preconditioner on a variety of devices in terms of iterations, storage, and run time.
Virtual damping and Einstein relation in oscillators
 IEEE Journal of SolidState Circuits
, 2003
"... Abstract—This paper presents a new physical theory of oscillator phase noise. Built around the concept of phase diffusion, this work bridges the fundamental physics of noise and existing oscillator phasenoise theories. The virtual damping of an ensemble of oscillators is introduced as a measure of ..."
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Cited by 6 (1 self)
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Abstract—This paper presents a new physical theory of oscillator phase noise. Built around the concept of phase diffusion, this work bridges the fundamental physics of noise and existing oscillator phasenoise theories. The virtual damping of an ensemble of oscillators is introduced as a measure of phase noise. The explanation of linewidth compression through virtual damping provides a unified view of resonators and oscillators. The direct correspondence between phase noise and the Einstein relation is demonstrated, which reveals the underlying physics of phase noise. The validity of the new approach is confirmed by consistent experimental agreement. Index Terms—Analog integrated circuits, LC oscillators, oscillators, phase noise, radiofrequency (RF) circuits, resonators, ring oscillators. I.
Parameter Extraction for the Bipolar Transistor Model Mextram: Level 504
 level 504,” Unclassified Report NLUR 2001/801, Philips Nat.Lab., 2001. See Ref. [1
, 2001
"... Parameter extraction is an important part in the whole process of using a compact model. We describe a general way of extracting parameters for Mextram. This includes a description of the measurements that have to be taken. In general it is difficult to achieve... ..."
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Cited by 5 (4 self)
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Parameter extraction is an important part in the whole process of using a compact model. We describe a general way of extracting parameters for Mextram. This includes a description of the measurements that have to be taken. In general it is difficult to achieve...
Analytical Modeling and Reduction of Direct Tunneling Current during Behavioral Synthesis of Nanometer CMOS Circuits
 in Proceedings of the 14th ACM/IEEE International Workshop on Logic and Synthesis (IWLS
, 2005
"... Gate oxide direct tunneling current is the major component of static power dissipation of a CMOS circuit for lowend technology, where the gate dielectric (SiO 2 ) thickness is very low. This paper presents a novel direct tunneling current reduction method during behavioral synthesis of nanometer CM ..."
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Cited by 5 (5 self)
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Gate oxide direct tunneling current is the major component of static power dissipation of a CMOS circuit for lowend technology, where the gate dielectric (SiO 2 ) thickness is very low. This paper presents a novel direct tunneling current reduction method during behavioral synthesis of nanometer CMOS circuits. We provide analytical models to calculate the direct tunneling current and the propagation delay of behavioral level components. We then characterize those components for various gate oxide thicknesses. We also provide an algorithm for behavioral scheduling for minimizing the overall tunneling current dissipation of datapath circuits. The algorithm explores dual oxide thickness option for reducing direct tunneling current. We have carried out extensive experiments for various behavioral level benchmarks under various resource constraints and observed significant reductions in tunneling current.
Optimal Control of the Drift Diffusion Model for Semiconductor Devices
, 2000
"... . The design problem for semiconductor devices is studied via an optimal control approach for the standard drift diusion model. The solvability of the minimization problem is proved. The rst{order optimality system is derived and the existence of Lagrange{multipliers is established. Further, esti ..."
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Cited by 5 (1 self)
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. The design problem for semiconductor devices is studied via an optimal control approach for the standard drift diusion model. The solvability of the minimization problem is proved. The rst{order optimality system is derived and the existence of Lagrange{multipliers is established. Further, estimates on the sensitivities are given. Numerical results concerning a symmetric n{p{diode are presented. 1.
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
 in Proceedings of the 19th IEEE International Conference on VLSI Design (VLSID), 2006
, 2006
"... Abstract — For a nanoCMOS of sub65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation delay of behavioral level component ..."
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Cited by 4 (4 self)
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Abstract — For a nanoCMOS of sub65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we provide analytical models to describe the tunneling current and propagation delay of behavioral level components considering various physical effects in the absence of foundry data. Subsequently, we explore the use of multiple oxide thickness resources as a technique for the reduction of gate leakage. In particular, we introduce a behavioral datapath scheduler that maximizes the utilization of higher gate oxide thickness resources. We characterize behavioral components for both 65nm and 45nm technologies in order to study the trend of tunneling current as technology scales, and provide them as inputs to the scheduler. We carried out extensive experiments for several benchmarks and observed significant reduction in gate leakage. I.
I_DDXBased Test methods: A Survey
 ACM Trans. Design Automation of Electronic Systems
, 2004
"... This paper presents a survey of the research reported in the literature to extend the use of I DDX tests to deep submicron (DSM) technologies ..."
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Cited by 4 (0 self)
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This paper presents a survey of the research reported in the literature to extend the use of I DDX tests to deep submicron (DSM) technologies