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With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large onchip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that the branch predictor is a thermal hot spot, thus further increasing its leakage. For these reasons, it is natural to consider applying decay techniques---already shown to reduce leakage energy for caches---to branch-prediction structures.

This paper evaluates design options related to these questions

Branch prediction is the main method of providing speculative opportunities for new high performance processors, therefore the accuracy of branch prediction is becoming very important. Motivated by this desire to achieve high levels of branch prediction, this study examines methods of using up to 24 bits branch direction history to determine the probable outcome of the next execution of a conditional branch. Using profiling to train a prediction logic function achieves an average branch prediction accuracy of up to 96.9% for the six benchmarks used in this study. Key Words and Phrases: Branch prediction, Trained branch prediction, Adaptive branch prediction Copyright c fl 1993 by John D. Johnson Contents 1 Introduction 1 2 Methodology, Tools and Benchmarks 2 3 Accuracy of the Prediction Functions 5 3.1 Optimal Static Branch Prediction : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 3.2 Population Count Prediction Logic : : : : : : : : : : : : : : : : : : : : : : : : : ...

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