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15
Optimization of Custom MOS Circuits by Transistor Sizing
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1996
"... Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to r ..."
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Cited by 11 (5 self)
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design highperformance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses
Reducing the Parallel Solution Time of Sparse Circuit Matrices Using Reordered Gaussian Elimination and Relaxation
 In Proc. International Symposium on Circuits and Systems
, 1988
"... Using irallel processors to reduce the execution times of classical cir cuit simulation programs like $PIGE and ASTAP has been the fcus of much current research. In these efforts, good parallel speed increases have been achieved for linearized system construction, but it has been difficult to g ..."
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Cited by 5 (0 self)
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Using irallel processors to reduce the execution times of classical cir cuit simulation programs like $PIGE and ASTAP has been the fcus of much current research. In these efforts, good parallel speed increases have been achieved for linearized system construction, but it has been difficult to get good. parallel speed increaSeS for sparse matrix solution.
From Circuit to Signal  development of a piecewise linear simulator
, 1993
"... vii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Samenvatting ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..."
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Cited by 1 (0 self)
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vii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Samenvatting ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Simulation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Modeling 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 PLATO 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Overview 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Piecewise Linear Modeling 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction 7 . . . . . . . . . ....
A Parallel BandMatrix Solver for a Circuit Simulation Problem
"... This report sumarizes and evaluates an implementation of a general bandmatrix solver algorithm on a massively parallel multiprocessor, the "Connection Machine". The band algorithm is used in a nonlinear relaxationbased circuit simulator for solving the system of equations associated with ..."
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Cited by 1 (1 self)
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This report sumarizes and evaluates an implementation of a general bandmatrix solver algorithm on a massively parallel multiprocessor, the "Connection Machine". The band algorithm is used in a nonlinear relaxationbased circuit simulator for solving the system of equations associated with the node voltages, at each Newton iteration at each time step. Acknowledgments This report is part of the requisites for course 18.435/6.848, taught by Prof. F. Thomson Leighton at the Massachusetts Institute of Technology in the Fall Term of 1988. I thank Andrew Lumsdaine who wrote the original sequential version of the simulator and did most of the circuit element models for the "Connection Machine" version. Toghether, we worked out the data structures we used and defined the global simulation control structure. Without his help and cooperation this work would not have been made. I acknowledge the cooperation of Prof. Leighton over all phases of the implementation by providing important suggesti...
ADAPTATION OF "SPICE3" TO SIMULATION OF LOSSY MULTIPLECOUPLED TRANSMISSION LINES
"... Design of highspeed, highperformance electronic circuits require simulation of transients in networks that include multiple, coupled lossy transmission lines. Widely used circuit simulator, SPICE, does not have facilities for simulation of multiconductor transmission lines. Recently a modificatio ..."
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Design of highspeed, highperformance electronic circuits require simulation of transients in networks that include multiple, coupled lossy transmission lines. Widely used circuit simulator, SPICE, does not have facilities for simulation of multiconductor transmission lines. Recently a modification to SPICE3 to include multiconductor lossless lines was reported [6]. In many situations line losses must be included in the model and networks with lossy transmission simulated. In general simulation of lossy transmission lines is complex and computationally very intensive. Situation is simpler when DC losses are considered. Recent studying [7] concluded that DC losses provide an adequate modeling of signal transmission in many practical situations. This paper describes the implementation of multiconductor, coupled lines with DC losses in SPICE3e2. Internal tests of the new program, LSPICE3, were successfully performed and now program is available to SPICE3 users.
ANALOG/DIGITAL CIRCUITS
, 1995
"... The increasing use of mixed signal circuits with analog and digital circuitry on the same lchip have created a set of demands that traditional circuit simuiators cannot meet very well. We pmsent techniques to efficiently handle the simulation of mixed signal analog/digital circuits, ad SYMPHONY, a ..."
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The increasing use of mixed signal circuits with analog and digital circuitry on the same lchip have created a set of demands that traditional circuit simuiators cannot meet very well. We pmsent techniques to efficiently handle the simulation of mixed signal analog/digital circuits, ad SYMPHONY, a fast mixedsignal simulator which embodies them. SYMPHONY combines a fast simulator for digital circuits with a traditional nonlinear slolver a la SPICE for the analog subcircuits. The digital simulator uses Stepwise Equivalence Conductance to model nonlinear device conductances and Piecewise Linear voltage waveforms. Device kharacteristics of bipolar elements in digital subcircuits are modeled by a Piecewise Linear apprbximation using the Extended Chebyshev Points, such that the worst case approximation error is @himized. Dynamic circuit partitioning is used to fully exploit the latency and multirate behavior Of the circuit. The simulator is implemented in an eventdriven framework with local and global docks for even management. A set of benchmark results are presented on a suit of BiMOS circuits, A transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits is also presented. The proposed approach use $ stepwise
Macromodeling CMOS Circuits for Timing Simulation Signature of Author Certified by Accepted by
, 1987
"... A macromodeling and timing simulation technique is presented that allows fast, accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic ..."
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A macromodeling and timing simulation technique is presented that allows fast, accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. For logic gates, output transition time and delay time are functions of input transition time and load impedance. Effective resistances for conducting transmission gates and switching transmission gates are functions of input transition time and load capacitance. Transmission gate circuits are then modeled as equivalent RC circuits. Separate waveform models and delay calculation methods exist for both types of circuit forms, with an interface to enable the use of both methods in the same simulation. An experimental eventdriven simulator was developed to test the accuracy of the macromodels and to estimate improvements in execution time with respect to SPICE. Typical delay times were within 5 % for logic gate circuits and 10 % for transmission gate circuits when compared with SPICE. The execution time of the experimental simulator
Performance Tuning of a Multiprocessor Sparse Matrix Equation Solver
"... Solving a system of linear simultaneous equations representing an electrical circuit is one of the most time consuming tasks for large scale circuit simulations. In order to facilitate a multiprocessor implementation of the circuit simulation program SPICE, a decomposition algorithm is employed to p ..."
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Solving a system of linear simultaneous equations representing an electrical circuit is one of the most time consuming tasks for large scale circuit simulations. In order to facilitate a multiprocessor implementation of the circuit simulation program SPICE, a decomposition algorithm is employed to partition the sparse matrix equution qf an overall circuit into a number of subcircuit equations for parallel processing. In this paper, various implementation and performance tuning issues of a parallel direct method matrix equation solving routine is reported This routine is written in such a manner that the data structure is compatible with SPICE Version 3CI. The speedup obtained for the simulation of several test circuits on a message passing multiprocessor system built on Transputers will be reported.
Parallelizing Circuit Simulation  A Combined Algorithmic And Specialized Hardware Approach
"... Accurate performance estimation of highdensity integrated circuits requires the kind of detailed numerical simulation performed in programs like ASTAP[1] and SPICE[2]. Because of the large computation time required for such prograins when applied to large circuits, accelerating numerical simulation ..."
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Accurate performance estimation of highdensity integrated circuits requires the kind of detailed numerical simulation performed in programs like ASTAP[1] and SPICE[2]. Because of the large computation time required for such prograins when applied to large circuits, accelerating numerical simulation is an important problem. Parallel processing promises to be a viable approach to accclerating the simulation of large circuits. This paper presents an approach which exploits the parallelism in the simulation problem at two levels. A relaxation algorithm is used to break the circuit into loosely coupled blocks which can be computed in parallel, and spe cial purpose hardware is used to exploit parallelism inside the block computation.
The Frequency Domain Behavioral Modeling and Simulation of Nonlinear Analog Circuits and Systems
, 1993
"... LUNSFORD II, PHILIP J. The Frequency Domain Behavioral Modeling and Simulation of Nonlinear Analog Circuits and Systems. (Under the direction of Michael B. Steer.) A new technique for the frequencydomain behavioral modeling and simulation of nonautonomous nonlinear analog subsystems is presented. ..."
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LUNSFORD II, PHILIP J. The Frequency Domain Behavioral Modeling and Simulation of Nonlinear Analog Circuits and Systems. (Under the direction of Michael B. Steer.) A new technique for the frequencydomain behavioral modeling and simulation of nonautonomous nonlinear analog subsystems is presented. This technique extracts values of the Volterra nonlinear transfer functions and stores these values in binary files. Using these files, the modeled substem can be simulated for an arbitrary periodic input expressed as a finite sum of sines and cosines. Furthermore, the extraction can be based on any circuit simulator that is capable of steady state simulation. Thus a large system can be divided into smaller subsystems, each of which is characterized by circuit level simulations or lab measurements. The total system can then be simulated using the subsystem characterization stored as tables in binary files.