Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses

Using irallel processors to reduce the execution times of classical cir- cuit simulation programs like $PIGE and ASTAP has been the fcus of much current research. In these efforts, good parallel speed increases have been achieved for linearized system construction, but it has been difficult to get good. parallel speed increaSeS for sparse matrix solution.

vii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Samenvatting ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preface xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Simulation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Modeling 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 PLATO 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Overview 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Piecewise Linear Modeling 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction 7 . . . . . . . . . ....

This report sumarizes and evaluates an implementation of a general band-matrix solver algorithm on a massively parallel multiprocessor, the "Connection Machine". The band algorithm is used in a nonlinear relaxation-based circuit simulator for solving the system of equations associated with the node voltages, at each Newton iteration at each time step. Acknowledgments This report is part of the requisites for course 18.435/6.848, taught by Prof. F. Thomson Leighton at the Massachusetts Institute of Technology in the Fall Term of 1988. I thank Andrew Lumsdaine who wrote the original sequential version of the simulator and did most of the circuit element models for the "Connection Machine" version. Toghether, we worked out the data structures we used and defined the global simulation control structure. Without his help and cooperation this work would not have been made. I acknowledge the cooperation of Prof. Leighton over all phases of the implementation by providing important suggesti...

Keywords - Electrical Circuit Simulation, Explicit Methods, Exponential Fitting Explicit Methods, Parallel Processing Computer Architectures, ESPRIT 1058 project, CINNAMON Circuit Simulation is nowadays a well established technique for the verification of electronic circuits performance and functionality. The simulation process can be carried out at different levels corresponding to the detail used in modeling the functionality of the devices present in a circuit. Through the process of simulation, it becomes possible to detect errors in the design phase of a project, which, due to the complexity and cost of present circuits, represents a minimization of the financial and human effort dedicated to design development. Electrical Circuit Simulation models devices at a very detailed level. Based on the constitutive equations of the elements and the topology of their interconnections, it uses numerical tools of high complexity to solve the resulting circuit equations. Due to the increasing...

The history of semiconductor chips has been characterized by a steady growth in the level of integration. Although this growth has given computer designers more capable circuits, it has become increasingly difficult to ensure highly reliable designs. Until now, the reliability of semiconductor chips has been parametrized by the logic family; the operating voltage, temperature, and environment; and the level of integration of the component. Thus, to obtain highly reliable systems, it was often necessary to limit the number of transistors. An attractive and potentially important extension to the analysis of circuit reliability is to account for the connectivity of the individual internal components. For circuits in Complementary Metal Oxide Silicon (cmos) technology, this reliability analysis is accomplished by modeling open and shorted transistors, "stuck--at" wires, and failed power and ground sources. Direct analysis of the reliability of a circuit by exhaustive enumeration of all fau...

LUNSFORD II, PHILIP J. The Frequency Domain Behavioral Modeling and Simulation of Nonlinear Analog Circuits and Systems. (Under the direction of Michael B. Steer.) A new technique for the frequency-domain behavioral modeling and simulation of nonautonomous nonlinear analog subsystems is presented. This technique extracts values of the Volterra nonlinear transfer functions and stores these values in binary files. Using these files, the modeled substem can be simulated for an arbitrary periodic input expressed as a finite sum of sines and cosines. Furthermore, the extraction can be based on any circuit simulator that is capable of steady state simulation. Thus a large system can be divided into smaller subsystems, each of which is characterized by circuit level simulations or lab measurements. The total system can then be simulated using the subsystem characterization stored as tables in binary files.

Accurate performance estimation of high-density integrated circuits requires the kind of detailed numerical simulation performed in programs like ASTAP[1] and SPICE[2]. Because of the large computation time required for such prograins when applied to large circuits, accelerating numerical simulation is an important problem. Parallel processing promises to be a viable approach to accclerating the simulation of large circuits. This paper presents an approach which exploits the parallelism in the simulation problem at two levels. A relaxation algorithm is used to break the circuit into loosely coupled blocks which can be computed in parallel, and spe- cial purpose hardware is used to exploit parallelism inside the block computation.

Design of high-speed, high-performance electronic circuits require simulation of transients in networks that include multiple, coupled lossy transmission lines. Widely used circuit simulator, SPICE, does not have facilities for simulation of multi-conductor transmission lines. Recently a modification to SPICE3 to include multi-conductor lossless lines was reported [6]. In many situations line losses must be included in the model and networks with lossy transmission simulated. In general simulation of lossy transmission lines is complex and computationally very intensive. Situation is simpler when D-C losses are considered. Recent studying [7] concluded that D-C losses provide an adequate modeling of signal transmission in many practical situations. This paper describes the implementation of multi-conductor, coupled lines with D-C losses in SPICE3e2. Internal tests of the new program, LSPICE3, were successfully performed and now program is available to SPICE3 users.