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39
minimization in IC Design: Principles and applications
 ACM Transactions on Design Automation of Electronic Systems
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 159 (29 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems. 1.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 57 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
SkewTolerant Circuit Design
, 1999
"... As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive system ..."
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Cited by 23 (2 self)
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As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive systems. Fortunately, the designer can hide much of this overhead through better design techniques. The key to skewtolerant design is avoiding hard edges in which data must setup before a clock edge but will not continue propagating until after the clock edge. Skewtolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead.
Hybrid structured clock network construction
 Proceedings of the 2001 IEEE/ACM international conference on Computeraided design
, 2001
"... This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, us ..."
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Cited by 17 (0 self)
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This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zeroskew clock meshes, with underlying zeroskew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a postprocessing step, wire width optimization under an accurate higherorder delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree. 1.
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 17 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
A Fresh Look at Retiming via Clock Skew Optimization
, 1995
"... The introduction of clockskew at an edgetriggered flipflop has an effect that is similar to the movement of the flipflop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, f ..."
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Cited by 16 (2 self)
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The introduction of clockskew at an edgetriggered flipflop has an effect that is similar to the movement of the flipflop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this work, for the first time, utilizes this information to find a minimum/specified period retiming efficiently. The clock period is guaranteed to be at most one gate delay larger than a tight lower bound on the optimal clock period; this bound is achievable using a combination of intentional skew and retiming. All ISCAS89 circuits can be retimed in a few minutes by this algorithm.
Boundedskew clock and steiner routing under elmore delay
 UCLA Computer Science Department
, 1995
"... Abstract: We study the minimumcost boundedskew routing tree problem under the Elmore delay model. We present two approaches to construct boundedskew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to theboundariesof merging regi ..."
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Cited by 15 (4 self)
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Abstract: We study the minimumcost boundedskew routing tree problem under the Elmore delay model. We present two approaches to construct boundedskew routing trees: (i) the Boundary Merging and Embedding (BME) method which utilizes merging points that are restricted to theboundariesof merging regions, and (ii) the Interior Merging and Embedding (IME) algorithm which employs a sampling strategy and dynamic programming to consider merging points that are interior to, rather than on the boundary of, the merging regions. Our new algorithms allow accurate control of Elmore delay skew, and show the utility of merging points inside merging regions. 1
UST/DME: a clock tree router for general skew constraints
 In Proceedings of the IEEE/ACM International Conference on ComputerAided Design
, 2000
"... tsao @ ultimatech.com In this paper, we propose new approaches for solving the usefulskew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferredmerge embedding (DME) paradigm for zeroskew ..."
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Cited by 15 (4 self)
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tsao @ ultimatech.com In this paper, we propose new approaches for solving the usefulskew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST algorithms is based on the deferredmerge embedding (DME) paradigm for zeroskew tree [5; 11 and boundedskew tree [8; 21 routings; hence, the names UST/DME and GreedyUST/DME for our algorithms. They simultaneously perform skew scheduling and tree routing such that each local skew range is incrementally refined to a skew value that minimizes the wirelength during the bottomup merging phase of DME. The resulting skew schedule is not only feasible, but is also best for routing in terms of wirelength. The experimental results show very encouraging improvement over the previous BSTIDME algorithm on three ISCAS89 benchmarks under general skew constraints in terms of total wirelength. 1.
An efficient zeroskew routing algorithm
 in Proc. ACM/IEEE Design Automation Conf
, 1994
"... Abstract  A bucket algorithm is proposed for zeroskew routing with linear time complexity on the average. Our algorithm is much simpler and more e cient than the best known algorithm which uses Delaunay triangulations for segments on Manhattan distance. Experimental results show that the linearity ..."
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Cited by 13 (0 self)
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Abstract  A bucket algorithm is proposed for zeroskew routing with linear time complexity on the average. Our algorithm is much simpler and more e cient than the best known algorithm which uses Delaunay triangulations for segments on Manhattan distance. Experimental results show that the linearity of our algorithm is accomplished. Our algorithm generates a zeroskew routing for 3000pin benchmark data within 5 seconds on a 90MIPS RISC workstation. I.
Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization
 Proc. Int'l Conf. on ComputerAided Design
, 1995
"... An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycleborrow ..."
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Cited by 12 (0 self)
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An algorithm for unifying the techniques of gate sizing and clockskew optimization for acyclic pipelines is presented in this paper. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycleborrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycleborrowing using sizing+skew results in a better overall areadelay tradeoff than with sizing alone.