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Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 109 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 63 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
ZeroSkew Clock Routing Trees With Minimum Wirelength," technical report UCLA CSD920012
, 1992
"... In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of t ..."
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Cited by 58 (14 self)
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In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we present the DeferredMerge Embedding (DME) algorithm, which in linear time embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Extensive experimental results show that the algorithm yields exact zero skew trees with 9% to 16 % wirelength reduction over previous constructions [5] [6]. The DME algorithm may be applied to either the Elmore or the linear delay model, and yields optimal total wirelength for linear delay. 1
Clocking Design and Analysis for a 600MHz Alpha Microprocessor
 IEEE Journal of Solid State Circuits, Vol
, 1998
"... ..."
ClusteringBased Optimization Algorithm in ZeroSkew Routings
 Proc. ACM/IEEE Design Automation Conf
, 1993
"... A zeroskew routing algorithm with clustering and improvement methods is proposed. This algorithm generates a zeroskew routing in O(n log n) time for n pins, and it is proven that the order of the total wire length is best possible. Our algorithm achieves 20% reduction of the total wire length and ..."
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Cited by 51 (2 self)
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A zeroskew routing algorithm with clustering and improvement methods is proposed. This algorithm generates a zeroskew routing in O(n log n) time for n pins, and it is proven that the order of the total wire length is best possible. Our algorithm achieves 20% reduction of the total wire length and 15%50% improvement of the delay time on benchmark data compared with the best known algorithm. 1 Department of Computer Science, Princeton University and C&C Systems Research Laboratories, NEC Corporation 1 Introduction Designing zeroskew routings with minimal delay time is one of the most crucial issues in current and future performancedriven layouts. In synchronous circuits, the clock skew t skew limits the clock period t c together with data path delay t d and other constant factors t const . The following equation formulates the clock period: t c = t skew + t d + t const : Therefore, in order to optimize the clock period, the clock skew needs to be minimized. In addition, in desi...
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... Nonuniform thermal profiles on the substrate in highperformance ICs can significantly impact the performance of global onchip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encoun ..."
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Cited by 36 (2 self)
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Nonuniform thermal profiles on the substrate in highperformance ICs can significantly impact the performance of global onchip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperaturedependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zeroskew clock routing methodology is presented. This study suggests that thermallyaware analysis should become an integrated part of the various optimization steps in physicalsynthesis flow to improve the performance and integrity of signals in global ULSI interconnects.
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
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Cited by 30 (8 self)
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Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
SkewTolerant Circuit Design
, 1999
"... As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive system ..."
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Cited by 28 (2 self)
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As cycle times in highperformance digital systems shrink faster than simple process improvement allows, sequencing overhead consumes an increasing fraction of the clock period. In particular, the overhead of traditional domino pipelines can consume 25% or more of the cycle time in aggressive systems. Fortunately, the designer can hide much of this overhead through better design techniques. The key to skewtolerant design is avoiding hard edges in which data must setup before a clock edge but will not continue propagating until after the clock edge. Skewtolerant domino circuits use multiple overlapping clocks to eliminate latches, removing hard edges and hiding the sequencing overhead.
A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations
 IEEE Transactions on VLSI Systems
, 2002
"... The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume at least a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock ..."
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Cited by 24 (1 self)
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The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume at least a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at highlevel design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock subsystem and the total system power budget is assessed Index TermsClock powerconsumptionmodeling, digitalCMOS, phaselockedloop, VLSI lowpowerdesign.
MinimumCost BoundedSkew Clock Routing
 IEEE Intl. Symp. Circuits and Systems
, 1995
"... In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given pathlength skew bound. The algorithm constructs a boundedskew tree (BST) in two steps: (i) a bottomup phase to construct a binary tree of shortestdistance feasible regions which represent the ..."
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Cited by 21 (4 self)
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In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given pathlength skew bound. The algorithm constructs a boundedskew tree (BST) in two steps: (i) a bottomup phase to construct a binary tree of shortestdistance feasible regions which represent the loci of possible placements of clock entry points, and (ii) a topdown phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of routing solutions with skew and wirelength tradeoff. 1 Introduction Clock skew minimization is an important issue in the design of high performance circuits. Over the past few years, a number of clock routing algorithms have been proposed, including the Htree construction for regular systolic arrays [1], the method of means and medians (MMM) by [10], the recursive geometric matching method by [6], and exact zero skew routing under the Elmore delay model by [17]....