We describe SAFL, a call-by-value first-order functional language which is syntactically restricted so that storage may be statically allocated to fixed locations. Evaluation of independent sub-expressions happens in parallel - we use locking techniques to protect shared-use function definitions (i.e. to prevent unrestricted parallel accesses to their storage locations for argument and return values). SAFL programs have a well defined notion of total (program and data) size which we refer to as `area'; similarly we can talk about execution `time'. Fold/unfold transformations on SAFL provide mappings between different points on the area-time spectrum. The space of functions expressible in SAFL is incomparable with the space of primitive recursive functions, in particular interpreters are expressible. The motivation behind SAFL is hardware description and synthesis|we have built an optimising compiler for translating SAFL to silicon.

Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experience in a formal framework, both approaches are emerging as interdependent facets of design. The thesis of this work is that alternate forms of formal reasoning must be integrated if formal methods are to support the natural analytical and generative reasoning that takes place in engineering practice. As a vehicle for this research, the DDD digital design derivation system was implemented to study formal hardware design in an algebraic framework. DDD is a first-order transformation system which mechanizes a basic design algebra for synthesizing digital circuit descriptions from high-level functional specifications. The system is a collection of correctness preserving transformations that promote a topdown desig...

Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are first-class objects in Haskell. We are thus able to use modern programming language features, such as higher-order functions, polymorphism, type classes and laziness, in hardware descriptions. We present two rather different versions of Lava. One version realises the embedding by using monads to keep track of the information specified in a hardware description. The other version uses a new language construct, called observable sharing, which eliminates the need for monads so that descriptions are much cleaner. Adding observable sharing to Haskell is a non-conservative extension, meaning that some properties of Haskell are lost. We thus investigate to what extent we are still allowed to use a normal Haskell compiler or interpreter. We also introduce an embedded language for specifying properties. The use of this language is two-fold. On the one hand, we can use it to specify and later formally verify properties of the described circuits. On the other hand, we can use it to specify and randomly test properties of normal Haskell programs. As a bonus, since hardware descriptions are embedded in Haskell, we can also use it to test our circuit descriptions.

In previous work we have developed and prototyped a silicon compiler which translates a functional language (SAFL) into hardware. Here we present a SAFL-level program transformation which: (i) partitions a specification into hardware and software parts and (ii) generates a specialised architecture to execute the software part. The architecture consists of a number of interconnected heterogeneous processors. Our method allows a large design space to be explored by systematically transforming a single SAFL specification to investigate di#erent points on the area-time spectrum.

. We present an overview of a prototype system based on a functional language for developing regular array circuits. The features of a simulator, floorplanner and expression transformer are discussed and illustrated. INTRODUCTION Implementing algorithms on a regular array of processors has many advantages. Besides offering an efficient realisation of parallel structures, regular patterns of interconnections also provide an opportunity for simplifying their description and their development. Various approaches for regular array design have been proposed; examples include methods based on dependence graphs [5], recurrence equations [14], and algebraic techniques [16]. This paper presents an overview of a prototype system for regular array development. The system is based on ¯FP [15], a functional language with mechanisms for abstracting spatial and temporal iteration. These abstractions result in a succinct and precise notation for specifying designs. Moreover, the explicit representat...

the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication between parallel threads and π-calculus style channel passing is provided. SAFL+ is designed for hardware description and synthesis; a silicon compiler, translating SAFL+ into RTL-Verilog, has been implemented. By parameterising functions over both data and channels the SAFL+ fun declaration becomes a powerful abstraction mechanism unifying a range of structuring techniques treated separately by existing HDLs. We show how SAFL+ is implemented at the circuit level and define the language formally by means of an operational semantics. 1

We survey the work done so far in the FLaSH project (Functional Languages for Synthesising Hardware) in which the core ideas are (i) using a functional language SAFL to describe hardware computation; (ii) transforming SAFL programs using various meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining); and (iii) compiling the resultant program in a resource-aware manner (keeping the gross structure of the resulting program by a 1-1 mapping of function definitions to functional units while exploiting ease-of-analysis properties of SAFL to select an ecient mapping) into hierarchical RTL Verilog.

this paper develops such a scheme, called "hardware description with recursion equations" (abbreviated HDRE and pronounced as hydra). A designer using HDRE may describe a circuit using a simple set of primitive functions written in an underlying general purpose programming language, and the description itself is just a function written in that language. Executing a circuit description function provides its meaning --- its semantic content.

We describe data parallel list operations that exploit pair structure on lists and an algebra that relates them. We illustrate their use in applications such as FFTs, sorting, and dynamic network design, and show that optimal algorithms can often be derived. The operations have a natural implementation on hypercubes and related topologies, and also a geometric implementation as dynamic networks. Equations from the algebra can be used a transformation rules, so that software or hardware development can be done in a calculational way.

The FLaSH project concerns the development of a hardware synthesis system based around the idea of mapping a high-level functional specification language, SAFL, into hardware using sophisticated compiler technology. The system has two phases: first we transform SAFL programs using meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining) while remaining a high-level specification. After this the FLaSH compiler maps the resultant SAFL program into hardware in a resource-aware manner, that is we map separate functions into separate functional units; functions which are called twice now become shared functional units - accessed by multiplexers and possibly arbiters. The current compiler outputs hierarchical RTL Verilog. The first phase is user-guided. The second is completely automatic - it uses optimising compiler technology to insert arbiters for shared functional units and to insert intermediate register...