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Generating Netlists from Executable Circuit Specifications in a Pure Functional Language
 In Functional Programming Glasgow, SpringerVerlag Workshops in Computing
, 1992
"... It is easy to write a circuit specification in a pure functional language so that execution of the specification simulates the circuit. It's harder to make an executable specification generate the circuit's netlist without using impure language features. The difficulty is that a circuit specifica ..."
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Cited by 17 (2 self)
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It is easy to write a circuit specification in a pure functional language so that execution of the specification simulates the circuit. It's harder to make an executable specification generate the circuit's netlist without using impure language features. The difficulty is that a circuit specification evaluates to a graph isomorphic to the circuit, so the specification of a circuit with feedback will evaluate to a circular (or infinite) graph. That prevents a naive graph traversal algorithm written in a pure functional language from terminating. This paper solves the problem by requiring the circuit specification to name components explicitly. With suitable higher order functions, the naming can be achieved without placing an undue burden on the circuit designer. This approach clarifies the distinction between transformations that preserve both the behaviour and structure of a circuit and transformations that preserve the behaviour while possibly changing the structure. It a...
Overview of Hydra: A concurrent language for synchronous digital circuit design
 In Proceedings of the 16th International Parallel and Distributed Processing Symposium. IEEE Computer
, 2002
"... www.dcs.gla.ac.uk/∼jtod/ Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and ..."
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Cited by 12 (0 self)
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www.dcs.gla.ac.uk/∼jtod/ Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor.
A Logic Programming Framework for Combinational Circuit Synthesis
 In 23rd International Conference on Logic Programming (ICLP), LNCS 4670
, 2007
"... Abstract. Logic Programming languages and combinational circuit synthesis tools share a common “combinatorial search over logic formulae” background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. Whi ..."
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Cited by 4 (3 self)
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Abstract. Logic Programming languages and combinational circuit synthesis tools share a common “combinatorial search over logic formulae” background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. While benefiting from Prolog’s fast unification algorithm and builtin backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate LeafDAGs implementing a combinational circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising firstrunner, Strict Boolean Inequality “< ” together with constant function “1 ” also turns out to have small transistorcount implementations, competitive to NANDonly or NORonly libraries. As a practical outcome, a more realistic circuit synthesizer is implemented that combines rewritingbased simplification of (<, 1) circuits with exhaustive LeafDAG circuit search.
A Preliminary Case Study in a Methodology for Deriving Parallel Programs Using APMs
"... We present a methodology based on Abstract Parallel Machines (APMs) for deriving an executable parallel program from a highlevel specification. The specification is given initially in mathematical notation and then transformed into a functional specification which is not explicitly parallel. This i ..."
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We present a methodology based on Abstract Parallel Machines (APMs) for deriving an executable parallel program from a highlevel specification. The specification is given initially in mathematical notation and then transformed into a functional specification which is not explicitly parallel. This is refined through a sequence of intermediate executable programs in the functional language using equational reasoning. At many of the steps in this process there are decisions which need to be made producing a variety of possible derivation paths, leading to a range of possible implementations. Hence the final implementation can be in a variety of languages and for a variety of programming models and architectures. We illustrate the method with a simple case study: the summation of the columns of a triangular matrix using load balancing to improve performance. We use Haskell in the derivation and C+MPI as the target language, and show the intermediate steps in the derivation and the transfo...
Functional Pearl  Derivation of a Carry Lookahead Addition Circuit
, 2001
"... Using Haskell as a digital circuit description language, we transform a ripple carry adder that requires O(n) time to add two nbit words into an efficient carry lookahead adder that requires O(log n) time. The gain in speed relies on the use of parallel scan to calculate the propagation of carry bi ..."
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Using Haskell as a digital circuit description language, we transform a ripple carry adder that requires O(n) time to add two nbit words into an efficient carry lookahead adder that requires O(log n) time. The gain in speed relies on the use of parallel scan to calculate the propagation of carry bits efficiently. The main difficulty is that this scan cannot be parallelised directly since it is applied to a nonassociative function. Several additional techniques are needed to circumvent the problem, including partial evaluation and symbolic function representation. The derivation given here provides a formal correctness proof, yet it also makes the solution more intuitive by bringing out explicitly each of the ideas underlying the carry lookahead adder.
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
"... Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns t ..."
Abstract
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Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor. 1