Results 11 
19 of
19
A proofproducing hardware compiler for a subset of higher order logic
 Oxford University
, 2005
"... (authors listed in alphabetical order) Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a ‘synthesisable subset ’ of HOL function definitions to correctbyconstruction clocked synchronous hardware. ..."
Abstract

Cited by 2 (0 self)
 Add to MetaCart
(authors listed in alphabetical order) Abstract. Higher order logic (HOL) is a modelling language suitable for specifying behaviour at many levels of abstraction. We describe a compiler from a ‘synthesisable subset ’ of HOL function definitions to correctbyconstruction clocked synchronous hardware. The compiler works by theorem proving in the HOL4 system and goes through several phases, each deductively refining the specification to a more concrete form, until a representation that corresponds to hardware is deduced. It also produces a proof that the generated hardware implements the HOL functions constituting the specification. Synthesised designs can be translated to Verilog HDL, simulated and then input to standard design automation tools. Users can modify the theorem proving scripts that perform compilation. A simple example is adding rewrites for peephole optimisation, but all the theoremproving infrastructure in HOL4 is available for tuning the compilation. Users can also extend the synthesisable subset. For example, the core system can only compile tailrecursions, but a ‘thirdparty ’ tool linRec is being developed to automatically generate tail recursive definitions to implement linear recursions, thereby extending the synthesisable subset of HOL to include linear recursion. 1
Functional Design Using Behavioural and Structural Components
, 2002
"... In previous work we have demonstrated how the functional language SAFL can be used as a behavioural hardware description language. ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
(Show Context)
In previous work we have demonstrated how the functional language SAFL can be used as a behavioural hardware description language.
Verifying Temporal Properties in HWHume
"... H### is a modern formallydefined programming language targeted at safetycritical, resourcebounded systems. A key feature of H### is the clear separation between computation and coordination, achieved through a finitestateautomata based approach, where a purely functional computation layer is ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
H### is a modern formallydefined programming language targeted at safetycritical, resourcebounded systems. A key feature of H### is the clear separation between computation and coordination, achieved through a finitestateautomata based approach, where a purely functional computation layer is embedded into a reactive coordination layer that manages interactions between processes and with the external state. It is our contention that this design makes formal analysis more tractable than for more conventional programming languages, such as C and Java, and hardware description languages, like VHDL and Verilog, since the formal proof requirements for each layer can be cleanly separated. In particular, coordination properties may be established directly without the need for explicit abstraction away from underlying control structures. This paper describes the use of model checking to verify the correctness of H### software systems at the coordination layer. A specification language which captures correctness and temporal properties is created for H### and is exploited through application of the S### model checker. This approach to verifying Hume coordination has been successfully applied to a range of examples.
Erlang inspired Hardware
"... AbstractThe Erlang programming language is a concurrency oriented functional language, based on the notion of independent processes and uses message passing for communication between processes. It is specially adapted to the realization of highly reliable distributed systems. In this paper it is a ..."
Abstract
 Add to MetaCart
(Show Context)
AbstractThe Erlang programming language is a concurrency oriented functional language, based on the notion of independent processes and uses message passing for communication between processes. It is specially adapted to the realization of highly reliable distributed systems. In this paper it is analyzed the use of the Erlang's computational paradigm for the design and implementation of application specific heterogeneous computational systems. The main objective is to use for the low level implementation the same computational model used in high level view of the system. This will allow an easier and faster design space exploration and optimization.
for Sensor Networks
, 2005
"... Sensor networks present a number of novel programming challenges for application developers. Their inherent limitations of computational power, communication bandwidth, and energy demand new approaches to programming that shield the developer from lowlevel details of resource management, concurrenc ..."
Abstract
 Add to MetaCart
(Show Context)
Sensor networks present a number of novel programming challenges for application developers. Their inherent limitations of computational power, communication bandwidth, and energy demand new approaches to programming that shield the developer from lowlevel details of resource management, concurrency, and innetwork processing. To answer this challenge, this thesis presents a functional macroprogramming language called Regiment. The essential data model in Regiment is based on regions, which represent spatially distributed, timevarying collections of state. The programmer uses regions to define and manipulate dynamic sets of sensor nodes. A first compiler for Regiment has been constructed, which implements the essential core of the langugae on the TinyOS platform. This thesis presents the compiler as well as an intermediate language developed to serve as a Regiment compilation target.
The University of Kansas Composing Specifications Using Algebra Combinators
, 2006
"... Project Sponsor: National Science Foundation The need to understand effects of crosscutting concerns defines the essence of systemslevel design. Understanding the impacts of local design decisions on global requirements such as power consumption or security is mandatory for constructing correct sy ..."
Abstract
 Add to MetaCart
(Show Context)
Project Sponsor: National Science Foundation The need to understand effects of crosscutting concerns defines the essence of systemslevel design. Understanding the impacts of local design decisions on global requirements such as power consumption or security is mandatory for constructing correct systems. Unfortunately, domain specific models may be defined using different semantics making analysis difficulty. We define an algebra combinator that provide semantics for syntax, an algebra combinator defines a single model that embodies the composition of those specifications. Such composite models can then be used to understand the interaction of models from the original specification domains. 1
AVoCS 2005 Preliminary Version Automatic Formal Synthesis of Hardware from Higher Order Logic
"... Abstract A compiler is described that translates recursive function definitions in higher order logic to clocked synchronous hardware. Circuits are synthesised by formal proof mechanised in the HOL4 system. The logic terms representing hardware can be directly translated to Verilog HDL, simulated an ..."
Abstract
 Add to MetaCart
Abstract A compiler is described that translates recursive function definitions in higher order logic to clocked synchronous hardware. Circuits are synthesised by formal proof mechanised in the HOL4 system. The logic terms representing hardware can be directly translated to Verilog HDL, simulated and then input to standard design automation tools. The theorem proving scripts that perform compilation are extensible. A simple example is adding rewrites for peephole optimisation, but all the theoremproving infrastructure in HOL4 is available for tuning the compilation. The synthesisable subset can also be extended. For example, the core system can only compile tailrecursive function definitions, but a separate tool linRec is being developed to transform linear recursions to tail recursions, thereby extending the synthesisable subset to include linear recursion. 1 Introduction Our goal is to create correctbyconstruction hardware directly from mathematical specifications. The `synthesisable subset ' of logic is not intended to be fixed, but to grow as we do case studies. Currently, the compiler can automatically generate hardware to implement tail recursive function definitions. A typical example is the following iterative multiplyandaccumulate function: MultIter(m,n,acc) =
System Modeling and Transformational Design Refinement in ForSyDe
"... methodology is highlevel modeling and refinement of systemsonachip and embedded systems. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal designtransformation methods for a transparent refinement process of ..."
Abstract
 Add to MetaCart
(Show Context)
methodology is highlevel modeling and refinement of systemsonachip and embedded systems. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal designtransformation methods for a transparent refinement process of the system model into an implementation model that is optimized for synthesis. The main contribution of this paper is the ForSyDe modeling technique and the formal treatment of transformational design refinement. We introduce process constructors, that cleanly separate the computation part of a process from the synchronization and communication part. We develop the characteristic function for each process type and use it to define semantic preserving and design decision transformations. These transformations are characterized by name, the format of the original process network, the transformed process network, and a design implication. The implication expresses the relation between original and transformed process network by means of the characteristic function. The objective of the refinement process is a model that can be implemented cost efficiently. To this end, process constructors and processes have a hardware and software interpretation which shall facilitate accurate performance and cost estimations. In a study of a digital equalizer example, we illustrate the modeling and refinement process and focus in particular on refinement of the clock domain, communication refinement, and resource sharing. Index Terms—Formal methods, hardware/software codesign, modeling, systemonachip (SoC).
Development and Application of Design Transformations in ForSyDe ∗
"... The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal design transformation methods for a transparent refinement process of the system model into an ..."
Abstract
 Add to MetaCart
(Show Context)
The ForSyDe methodology has been developed for system level design. Starting with a formal specification model, that captures the functionality of the system at a high abstraction level, it provides formal design transformation methods for a transparent refinement process of the system model into an implementation model that is optimized for synthesis. The main contribution of this paper is the formal treatment of transformational design refinement. Using the formal semantics of ForSyDe processes we introduce the term characteristic function to be able to define and classify transformations as either semantic preserving or design decision. We also illustrate how we can incorporate classical synthesis techniques that have traditionally been used with control/dataflow graphs as ForSyDe transformations. Thus, our approach avoids discontinuities since it moves design refinement into the domain of the specification model. 1