Synchronous data-flow is a programming paradigm which has been successfully applied in reactive systems. In this context, it can be characterized as some class of static bounded memory data-flow networks. In particular, these networks are not recursively defined, and obey some kind of "synchronous" constraints (clock calculus). Based on Kahn's relationship between data-flow and stream functions, the synchronous constraints can be related to Wadler's listlessness, and can be seen as sufficient conditions ensuring listless evaluation. As a by-product, those networks enjoy efficient compiling techniques. In this paper, we show that it is possible to extend the class of static synchronous data-flow to higher order and dynamical networks, thus giving sense to a larger class of synchronous data-flow networks.

The Marching Cubes algorithm is a popular high-resolution isosurface extraction method used in volume data visualization. However, it is relatively computationally intensive making real-time operation on normal workstations a di cult goal when applied to large datasets. One solution is to transform the serial algorithm into a vector-parallel algorithm designed to exploit the potential computing power supplied by a supercomputer. In this paper, we presentanimplementation of the Marching Cubes that considers the inherent parallelism in the algorithm as well as the speci c characteristics of the pipelined CPU of a vector-parallel supercomputer (Cray C90). In our approach, we vectorize two time-consuming operations in the Marching Cubes. The rst operation is the interpolation of the intersection points between the isosurface and the cube edges. The second vectorized operation is the computation of topological equivalences for classes of intersections. In this paper, we describe the details of our parallel algorithm and present the experimental results for several typical volume datasets. 1

Reconfigurable logic devices such as the FPGA have brought about a revolution in the field of hardware design. The reduction in development costs has had a huge impact on broadening the scope of applications for which a hardware implementation is a realistic possibility. Current FPGA devices run to many millions of gates, giving a huge potential for efficiency gains, benefiting from the inherently parallel nature of hardware circuits. These devices continue to grow in size, to the end that we can now seriously consider implementing even large scale systems purely in reconfigurable logic. Despite these advances, we find ourselves somewhat lacking in the tools and methodologies required to fully exploit this potential. Issues of hardware implementation and parallelism intro-duce significant complexity into the design process. We argue that without the correct approach, not only will this potential be under used, but the inherent complexity will undermine people’s