This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. The synthesis process produces a netlist of electronic components that are selected from a component library and sized such that the overall area is minimized and the rest of the performance constraints such as power, slew-rate, bandwidth, etc. are met. The gap between system level specifications and implementations is bridged using a hierarchically-organized, design-space exploration methodology. Our methodology performs a two-layered synthesis, the first being architecture generation, and the other component synthesis and constraint transformation. For architecture generation we suggest a branch-and-bound algorithm, while component synthesis and constraint transformation use a Genetic Algorithm based heuristic method. Crucial to the success of our exploration methodology is a fast and accurate performance est...

Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

In this paper, we present a technique for characterizing CMOS analog circuits based on directed intervals. The technique consists of an analog performance estimator and a characterization table generator. This characterization information may be efficiently used by the constraint transformation step in an analog synthesis system. We present a genetic algorithm based constraint transformation method, that exploits problem structure by using the circuit characterization information. We discuss the design of the genetic operators that capture the characteristics of the constraint transformation problem. The constraint transformation method that uses the characterization information was compared against one using a conventional genetic algorithm and the experimental results obtained demonstrate the effectiveness of the proposed approach. 1 Introduction Automatic synthesis tools that transform the description of a system at a higher-level of abstraction to a lower level typically consist...

This paper presents a behavioral representation for the class of Nyquist rate A/D converters that captures the nominal behavior, as well as all the statistical variations. To describe noise effects we use a joint probability density function. To describe behavioral effects due to process variations we use a covariance matrix, \Sigma t . Applications of the model include identification of important A/D error sources, efficient computation of the distributions of integral nonlinearity (INL) and differential nonlinearity (DNL), signal-to-noise plus distortion ratio (TSNR), and efficient worst case and Monte Carlo system simulations. Finally, parameter extraction results are presented that agree well with actual measurements. 1 Introduction The verification of data converters poses a significant challenge to the design community, partly due to the need for higher yield at high resolutions, and partly due to the emphasis on predicting converter performance when used in a system since more ...

In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottom-up one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented. 1. Introduction and Motivation Crucial to a top--down mixed--signal design process [12] is a mechanism to propagate the specifications and constraints on the design elements used at one level to those at the next level. This task of transforming the system-level specifications onto component level constraints is c...

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

In this paper, we present a constraint transformation and topology selection methodology that explores the system level parameter space to compute acceptable regions in the component parameter space. The search process of an underlying circuit synthesis tool could be confined to these regions of valid solutions. Experimental results showing the impact of parameter space exploration at a higher level on analog circuit synthesis are presented, demonstrating the effectiveness of this technique. 1 Introduction Crucial to a top-down analog design process [10] is an interfacing mechanism to communicate the specifications and constraints on the design elements used at one level with those at the next level. The task of transforming the high-level specifications onto module parameters is called Constraint Transformation [3]. Efficient automation of this task is one of the the most important steps in automating the design of analog and mixed analog-digital systems. There are two important asp...

In this paper we present a technique for constraint allocation in analog system synthesis. Constraint allocation is the process of assigning constraint budgets to the subsystems so that the user asserted system level constraints are satisfied. Our approach is based on the formulation of the constraint allocation problem as a constraint satisfaction problem (CSP) and solving it. The solution method employed uses interval techniques to check for the satisfiability of the CSP. The generation of the exact set of solutions is done by an interval reduction and instantiation mechanism. We also discuss the constraint allocation mechanism in the context of a mixed-signal synthesis system. Finally, we present a design example to validate the constraint allocation technique. 1 Introduction Constraint allocation is an important step in analog system synthesis. Given the system level constraints, constraint allocation refers to the process of assigning constraint budgets to each of the components...