We study efficient implementations of the push-relabel method for the maximum flow problem. The resulting codes are faster than the previous codes, and much faster on some problem families. The speedup is due to the combination of heuristics used in our implementation. We also exhibit a family of problems for which all known methods seem to have almost quadratic time growth rate.

Recently, several new algorithms have been developed for the minimum cut problem. These algorithms are very different from the earlier ones and from each other and substantially improve worst-case time bounds for the problem. We conduct experimental evaluation the relative performance of these algorithms. In the process, we develop heuristics and data structures that substantially improve practical performance of the algorithms. We also develop problem families for testing minimum cut algorithms. Our work leads to a better understanding of practical performance of the minimum cut algorithms and produces very efficient codes for the problem.

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In this paper, we study network flow algorithms for bipartite networks. A network G = (V; E) is called bipartite if its vertex set V can be partitioned into two subsets V 1 and V 2 such that all edges have one endpoint in V 1 and the other in V 2 . Let n = jV j, n 1 = jV 1 j, n 2 = jV 2 j, m = jEj and assume without loss of generality that n 1 n 2 . We call a bipartite network unbalanced if n 1 ø n 2 and balanced otherwise. (This notion is necessarily imprecise.) We show that several maximum flow algorithms can be substantially sped up when applied to unbalanced networks. The basic idea in these improvements is a two-edge push rule that allows us to "charge" most computation to vertices in V 1 , and hence develop algorithms whose running times depend on n 1 rather than n. For example, we show that the two-edge push version of Goldberg and Tarjan's FIFO preflow push algorithm runs in O(n 1 m + n 3 1 ) time and that the analogous version of Ahuja and Orlin's excess scaling algori...

We present a simple sequential algorithm for the maximum flow problem on a network with n nodes, m arcs, and integer arc capacities bounded by U. Under the practical assumption that U is polynomially bounded in n, our algorithm runs in time O(nm + n 2 log n). This result improves the previous best bound of O(nm log(n 2 /m)), obtained by Goldberg and Taran, by a factor of log n for networks that are both nonsparse and nondense without using any complex data structures. We also describe a parallel implementation of the algorithm that runs in O(n'log U log p) time in the PRAM model with EREW and uses only p processors where p = [m/n

We consider the problem of finding the minimum capacity cut in a directed network G with n nodes. This problem has applications to network reliability and survivability and is useful in subroutines for other network optimization problems. One can use a maximum flow problem to find a minimum cut separating a designated source node s from a designated sink node t, and by varying the sink node one can find a minimum cut in G as a sequence of at most 2n- 2 maximum flow problems. We then show how to reduce the running time of these 2n- 2 maximum flow algorithms to the running time for solving a single maximum flow problem. The resulting running time is O(nm log(n 2 /m)) for finding the minimum cut in either a directed or an undirected network. © 1994 Academic Press, Inc. 1.

Abstract. This report studies the global minimization of discretized total variation (TV) energies with an L p (in particular, L 1 and L 2) fidelity term using parametric maximum flow algorithms to minimize s-t cut representations of these energies. The TV/L 2 model, also known as the Rudin-Osher-Fatemi (ROF) model is suitable for restoring images contaminated by Gaussian noise, while the TV/L 1 model is able to remove impulsive noise from grey-scale images, and perform multi-scale decompositions of them. Preliminary numerical results on large-scale two-dimensional CT and three-dimensional Brain MR images are presented to illustrate the effectiveness of these approaches.

High-performance hardware designs often intersperse combinational logic freely between levelsensitive latch layers (wherein each layer is transparent during only one clock phase), rather than utilizing master-slave latch pairs with no combinational logic between. While such designs may generally achieve much faster clock speeds, this design style poses a challenge to verification. In particular, unless the k-phase netlist N is abstracted to a full-cycle register-based netlist N', verification of N requires k times (or greater) as many state variables as would be necessary to obtain equivalent verification of N'. We present algorithms to automatically identify and abstract k-phase netlists—i.e., to perform phase abstraction—by selectively eliminating latches. The abstraction is valid for model checking CTL∗ formulae which reason solely about latches of a single phase. This algorithm has been implemented in the model checker RuleBase, and used to enhance the model checking of IBM’s Gigahertz Processor, which would not have been feasible otherwise due to computational constraints. This abstraction has furthermore allowed verification engineers to write properties and environments more efficiently.

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