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A CMOS frequency synthesizer with an injectionlocked frequency divider for a 5GHz wireless LAN receiver
 IEEE J. SolidState Circuits
, 2000
"... based frequency synthesizer is designed in a H PR m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injectionlocked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. Onchip spiral inductors with patterned ground ..."
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Cited by 12 (1 self)
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based frequency synthesizer is designed in a H PR m CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injectionlocked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. Onchip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of IHI dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than SR dBc. Index Terms—CMOS RF circuits, frequency synthesizers, injectionlocked frequency dividers, wireless LAN. I.
An Accurate and Efficient High Frequency Noise Simulation Technique for Deep Submicron MOSFETs
, 2000
"... Based on an active transmission line concept and twodimensional (2D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and smallsignal equivalent circuit ..."
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Cited by 6 (3 self)
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Based on an active transmission line concept and twodimensional (2D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and smallsignal equivalent circuit of the MOSFET, three intrinsic noise parameters ( , , and )for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data. Index TermsMOSFETs, semiconductor device modeling, semiconductor device noise, simulation.
TECHNICAL LITERATURE The (Pre) History of the Integrated Circuit:
"... The halfcentury of the integrated circuit has witnessed so many technical miracles that perhaps engineers can be forgiven for being a little blase. But a little reflection should astonish even the most jaded: The silicon we use comes as giant monocrystals weighing hundreds of kilograms, and whose i ..."
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The halfcentury of the integrated circuit has witnessed so many technical miracles that perhaps engineers can be forgiven for being a little blase. But a little reflection should astonish even the most jaded: The silicon we use comes as giant monocrystals weighing hundreds of kilograms, and whose impurities are denominated in subparts per billion. On the wafers cut from these boules we regularly inscribe features with lateral dimensions of tens of nanometers (using light whose freespace wavelength is several times larger), and routinely grow layers with controlled thicknesses of only a few atoms. If those technical facts are too familiar, then perhaps a biological comparison will impress: The aggregate number of transistors produced annually exceeds the number of ants on Earth. For each of an estimated
CircuitBased Characterization of Device Noise Using Phase Noise Data
"... Abstract—A circuitbased device noise characterization technique is introduced which uses phase noise data to estimate the power spectral density (PSD) of highfrequency noise in MOSFETs. To apply this technique to a typical CMOS process, an oscillator structure is introduced which provides a predi ..."
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Abstract—A circuitbased device noise characterization technique is introduced which uses phase noise data to estimate the power spectral density (PSD) of highfrequency noise in MOSFETs. To apply this technique to a typical CMOS process, an oscillator structure is introduced which provides a predictable phase noise level for a given device noise PSD. The analytical equations governing the phase noise of this oscillator are presented and subsequently verified using circuit simulations. Three oscillators, using transistors of various channel lengths, are fabricated in a commercial 0.18 m CMOS process technology to study shortchannel excess noise. It is shown that, at equal current levels, the noise PSD in minimumchannellength transistors is 8.7 dB larger than that in 3minimumchannellength devices. The proposed method is especially suitable for applying to a stateoftheart CMOS process to provide a quantitative analysis of various noise tradeoffs which are sometimes missing in foundryprovided models. Index Terms—Device characterization, excess noise, integrated oscillator, jitter, MOSFET, noise, phase noise, ring oscillator, shortchannel effects.