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A Compressed BreadthFirst Search for Satisfiability
 Proc. 4th Workshop on Algorithm Engineering and Experiments
, 2002
"... Leading algorithms for Boolean satisfiability (SAT) are based on either a depthfirst tree traversal of the search space (the DLL procedure [6]) or resolution (the DP procedure [7]). In this work we introduce a variant of BreadthFirst Search (BFS) based on the ability of ZeroSuppressed Binary De ..."
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Leading algorithms for Boolean satisfiability (SAT) are based on either a depthfirst tree traversal of the search space (the DLL procedure [6]) or resolution (the DP procedure [7]). In this work we introduce a variant of BreadthFirst Search (BFS) based on the ability of ZeroSuppressed Binary Decision Diagrams (ZDDs) to compactly represent sparse or structured collections of subsets.
Resolution Cannot Polynomially Simulate CompressedBFS
 Ann. of Math. and A.I
, 2003
"... Many algorithms for Boolean satisfiability (SAT) work within the framework of resolution as a proof system, and thus on unsatisfiable instances they can be viewed as attempting to find proofs by resolution. However it has been known since the 1980s that every resolution proof of the pigeonhole princ ..."
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Cited by 4 (0 self)
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Many algorithms for Boolean satisfiability (SAT) work within the framework of resolution as a proof system, and thus on unsatisfiable instances they can be viewed as attempting to find proofs by resolution. However it has been known since the 1980s that every resolution proof of the pigeonhole principle (PHP n ), suitably encoded as a CNF instance, includes exponentially many steps [1]. Therefore SAT solvers based upon the DLL procedure [2] or the DP procedure [3] must take exponential time. Polynomialsized proofs of the pigeonhole principle exist for different proof systems, but generalpurpose SAT solvers often remain confined to resolution. This result is in correlation with empirical evidence. Previously, we introduced...
Simple yet efficient improvements of SAT based bounded model checking
 In: FMCAD. Volume 3312 of LNCS
, 2004
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Reducing Symmetries to Generate Easier SAT Instances
, 2005
"... Finding countermodels is an effective way of disproving false conjectures. In firstorder predicate logic, model finding is an undecidable problem. But if a finite model exists, it can be found by exhaustive search. The finite model generation problem in the firstorder logic can also be translated ..."
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Finding countermodels is an effective way of disproving false conjectures. In firstorder predicate logic, model finding is an undecidable problem. But if a finite model exists, it can be found by exhaustive search. The finite model generation problem in the firstorder logic can also be translated to the satisfiability problem in the propositional logic. But a direct translation may not be very efficient. This paper discusses how to take the symmetries into account so as to make the resulting problem easier. A static method for adding constraints is presented, which can be thought of as an approximation of the least number heuristic (LNH). Also described is a dynamic method, which asks a model searcher like SEM to generate a set of partial models, and then gives each partial model to a propositional prover. The two methods are analyzed, and compared with each other.
High speed layout synthesis for minimumwidth CMOS logic cells via Boolean satisfiability
 In Proc. of ASPDAC
, 2004
"... Abstract — This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes the highspeed layout synthesis for CMOS logic cells and guarantees to generate the minimum ..."
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Abstract — This paper proposes a cell layout synthesis method via Boolean Satisfiability (SAT). Cell layout synthesis problems are first transformed into SAT problems by our formulations. Our method realizes the highspeed layout synthesis for CMOS logic cells and guarantees to generate the minimum width cells with routability under our layout styles. It considers complementary P/NMOSFETs individually during transistor placement, and can generate smaller width layout compared with pairing the complementary P/NMOSFETs case. To demonstrate the effectiveness of our SATbased cell synthesis, we present experimental results which compare it with the 01 ILPbased transistor placement method and the commercial cell generation tool. The experimental results show that our SATbased method can generate minimum width placements in much shorter run time than the 01 ILPbased transistor placement method, and can generate the cell layouts of 32 static dual CMOS logic cirsuits in 54 % run time with only 3 % area increase compared with the commercial tool. I.
Improving firstorder model searching by propositional reasoning and lemma learning
 Proc. 7th Int’l Conf. on Theory and Applications of Satisfiability Testing
, 2004
"... Abstract. The finite model generation problem in the firstorder logic is a generalization of the propositional satisfiability (SAT) problem. An essential algorithm for solving the problem is backtracking search. In this paper, we show how to improve such a search procedure by lemma learning. For ef ..."
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Abstract. The finite model generation problem in the firstorder logic is a generalization of the propositional satisfiability (SAT) problem. An essential algorithm for solving the problem is backtracking search. In this paper, we show how to improve such a search procedure by lemma learning. For efficiency reasons, we represent the lemmas by propositional formulas and use a SAT solver to perform the necessary reasoning. We have extended the firstorder model generator SEM, combining it with the SAT solver SATO. Experimental results show that the search time may be reduced significantly on many problems. 1
Overcoming ResolutionBased Lower Bounds for SAT Solvers
"... Many leadingedge SAT solvers are based on the DavisPutnam procedure or the DavisLogemannLoveland procedure, and thus on unsatisfiable instances they can be viewed as attempting to find refutations by resolution. Therefore, exponential lower bounds on the length of resolution proofs also apply to ..."
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Many leadingedge SAT solvers are based on the DavisPutnam procedure or the DavisLogemannLoveland procedure, and thus on unsatisfiable instances they can be viewed as attempting to find refutations by resolution. Therefore, exponential lower bounds on the length of resolution proofs also apply to such solvers. Empirical performance of DLLbased solvers on SAT instances from the pigeonhole and Urquhart family are consistent with this expectation. Our work explores an entirely different approach to SAT solving that does not have this drawback. A barebones implementation of our algorithm, reported earlier, was able to refute pigeonhole instances in polynomial time without explicitly using symmetries, and this empirical result is backed up by an analytical proof. In this work, we show how to extend CompressedBFS to perform Boolean Constraint Propagation, part of all practical, complete SAT solvers. Unlike DLLbased solvers, our empirical results show that full BCP offers marginal improvements in runtime. 1.
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances
 In Proc. 7th International Conference on Theory and Applications of Satisfiability Testing (SAT
, 2004
"... The original algorithm for the SAT problem, Variable Elimination Resolution (VER/DP) has exponential space complexity. To tackle that, the backtracking based DPLL procedure [2] is used in SAT solvers. We present a combination of both of the techniques. We use NiVER, a special case of VER, to elimina ..."
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The original algorithm for the SAT problem, Variable Elimination Resolution (VER/DP) has exponential space complexity. To tackle that, the backtracking based DPLL procedure [2] is used in SAT solvers. We present a combination of both of the techniques. We use NiVER, a special case of VER, to eliminate some variables in a preprocessing step and then solve the simplified problem using a DPLL SAT solver. NiVER is a strictly formula size not increasing resolution based preprocessor. Best worstcase upper bounds for general SAT solving (arbitrary clause length) in terms of N (Number of variables), K (Number of clauses) and L (Literal count) are 2 , respectively [14]. In the experiments, NiVER resulted in upto 74% decrease in N , 58% decrease in K and 46% decrease in L. In many real life instances, we observed that most of the resolvents for several variables are tautologies. There will be no increase in space due to VER on them. Hence, despite its simplicity, NiVER does result in easier instances. In most of the cases, NiVER takes less than one second for preprocessing. In case NiVER removable variables are not present, due to very low overhead, the cost of NiVER is insignificant. We also study the e#ect of combining NiVER with HyPre [3], a preprocessor based on hyper binary resolution. Based on experimental results, we classify the SAT instances into 4 classes. NiVER consistently performs well in all those classes and hence can be incorporated into all general purpose SAT solvers.
On Proof Systems Behind Efficient SAT Solvers
, 2002
"... Conventional algorithms for Boolean satisfiability (SAT) work within the framework of resolution as a proof system. However it has been known since the 1980s that every resolution proof of the pigeonhole principle (PHP n ), suitably encoded as a CNF instance, includes exponentially many steps[4]. T ..."
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Conventional algorithms for Boolean satisfiability (SAT) work within the framework of resolution as a proof system. However it has been known since the 1980s that every resolution proof of the pigeonhole principle (PHP n ), suitably encoded as a CNF instance, includes exponentially many steps[4]. Therefore SAT solvers based upon the DLL procedure [1] or the DP procedure [2] must take exponential time. Polynomialsized proofs of the PHP exist for more powerful proof systems, but generalpurpose SAT solvers often remain confined to resolution.