A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from highlevel performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information. 1 Introduction The design of analog circuits is often a difficult task compared with a digital one of similar complexity because of the higher number of specifications and the importance of second order effects. In addition, the continuously growing complexity of analog integrated circuits has required a better control over the design quality and the redefinition of tasks like module generation and floorplanning. The performances of...

This paper describes a new approach to layout compaction of analog integrated circuits which respects all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. Our approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets.

As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and custom chips, however, it will soon become a concern in FPGAs. In this paper, we describe the first published erosstalk-aware router that targets FPGAs. We show that, in a representative FPGA architecture implemented in a 0.18gra technology, the average routing delay in the presence of crosstalk can be reduced by 7.1% compared to a router with no knowledge of crosstalk. About half of this improvement is due to a tighter delay estimator, and half is due to an improved routing algorithm, Categories and Subject Descriptors t3.7.2 [Integrated Circuits]: Design Aids-placement and routing.

Noise immunity is becomingone of the most important design parameters for deep-sub-micron (DSM) technologies. Asynchronous circuits seem to be a good candidate to alleviate the problemsoriginatedby simultaneousswitching noise. However, they are also more sensitive than synchronous ones to spurious signal transitions and delay variations produced by crosstalk noise. This paper addresses the problem of analyzing and synthesizing asynchronous circuits with noise immunity being the main design parameter. The techniques presented in the paper focus on cross talk noise and tackle the problem from the behavioral point of view.

Given the channel routing topology with k tracks, the problem of minimizing crosstalk is intractable, requiring O(k!) time even in the track-based permutation. In this paper, a new approach for track assignment enhancement, minimizing the signal crosstalk and defect areas between nets, while preserving the number of tracks, is presented. The approach is to allow for the split "nets" to be permuted for better crosstalk minimization, rather than simply permuting the tracks. We present a graph-based heuristic running in O( 2 ek2 2 \Gamma1 \Gamma ) time to obtain a near-optimal solution, where is the minimum clique cover number in an associated interval graph G and e is the number of edges in G. Here the parameter ( log k) provides a tradeoff between time complexity and solution quality. A noble split rainbow k-colour permutation algorithm is proposed based on a dynamic programming approach. Our experiments show a significant improvement; 6.4% (resp. 1%) for crosstalk and 32% (res...

In addition to automatically generating correct wiring, routers are used to meet additional design goals. Examples include reducing capacitive coupling and improving yield. Using routers to improve testability has been mentioned in the literature, but concrete rules or methods have not been explained or implemented. In this paper, we show how a modified router improves bridge fault testability for two different test metrics, static-voltage testing and pseudoexhaustive segmentation testing, with no significant increase in area or time. This method is flexible in that further testability improvements are possible by trading off area or routing time. 1 Introduction Modifications to the routing of a circuit can be made, either during or after the routing process, to meet secondary design goals. This has been shown and explored in several papers on reducing capacitive coupling [1--10] and improving yield [11--15]. What is common to these papers is that additional goals can be achieved by s...

We propose a technique to update dynamically the bounds used during constraint-driven routing. Moderate bound violations are allowed as long as no constraint violations are induced. Adaptive net scheduling is made possible during routing, so that nets requiring an implementation with large parasitics can take advantage of the margin made available to them by other parameters maintained within their own bounds. The user is provided with a quantitative evaluation of the effectiveness of the tool in enforcing the set of constraints on the given design. 1. Introduction The constraint-driven approach to layout [1] is based on the translation of performance constraints into a set of bounds for all layout parameters. A tool able to enforce all these bounds guarantees that high-level performance constraints are met. In general, an infinite number of feasible sets of bounds exist, and in order to determine the most suitable one, an optimization problem must be solved, usually referred to as "c...

ix Acknowledgments x 1. Introduction 1 2. Physical Design-For-Test Overview 3 2.1 Cell Modifications : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 2.1.1 Targeting Stuck-Open Faults : : : : : : : : : : : : : : : : : : : : : : 3 2.1.2 Local Transformations : : : : : : : : : : : : : : : : : : : : : : : : : : 4 2.2 Routing Modifications : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2.2.1 Routing and Placement Suggestions : : : : : : : : : : : : : : : : : : 6 2.2.2 Classifying Faults for P-DFT : : : : : : : : : : : : : : : : : : : : : : 7 2.2.3 P-DFT Based Upon Testability and Likelihood : : : : : : : : : : : : 8 2.2.4 Targeting Fanout-Free Regions : : : : : : : : : : : : : : : : : : : : : 8 2.3 Inductive Fault Analysis : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 3. Channel Routing Overview 10 3.1 Channel Routing in General : : : : : : : : : : : : : : : : : : : : : : : : : : : 10 3.1.1 Terminology : : : : : : : : : : : : : : : : : : : : ...

In this report I formulate analog layout constraints and survey the state of the art of automatic analog layout systems, which can handle only few analog constraints, and generate less dense layout. To solve these problems I propose a new interactive analog layout methodology. It provides topological editing in the geometrical view based on Rubber-band routing. The purposes of this new methodology are i) to overcome the difficulty of control the layout parasitic elements with irregularities of analog devices and wiring effects and ii) to reduce the analog VLSI design period. After describing new concepts for that interactive methodology, I state some specific challenges.