Results 1  10
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16
The Polynomial Method in Circuit Complexity
 In Proceedings of the 8th IEEE Structure in Complexity Theory Conference
, 1993
"... The representation of functions as lowdegree polynomials over various rings has provided many insights in the theory of smalldepth circuits. We survey some of the closure properties, upper bounds, and lower bounds obtained via this approach. 1. Introduction There is a long history of using polyno ..."
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Cited by 68 (4 self)
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The representation of functions as lowdegree polynomials over various rings has provided many insights in the theory of smalldepth circuits. We survey some of the closure properties, upper bounds, and lower bounds obtained via this approach. 1. Introduction There is a long history of using polynomials in order to prove complexity bounds. Minsky and Papert [39] used polynomials to prove early lower bounds on the order of perceptrons. Razborov [46] and Smolensky [49] used them to prove lower bounds on the size of ANDOR circuits. Other lower bounds via polynomials are due to [50, 4, 10, 51, 9, 55]. Paturi and Saks [44] discovered that rational functions could be used for lower bounds on the size of threshold circuits. Toda [53] used polynomials to prove upper bounds on the power of the polynomial hierarchy. This led to a series of upper bounds on the power of the polynomial hierarchy [54, 52], AC 0 [2, 3, 52, 19], and ACC [58, 20, 30, 37], and related classes [21, 42]. Beigel and Gi...
Simulating Threshold Circuits by Majority Circuits
 SIAM Journal on Computing
, 1994
"... We prove that a single threshold gate with arbitrary weights can be simulated by an explicit polynomialsize depth 2 majority circuit. In general we show that a depth d threshold circuit can be simulated uniformly by a majority circuit of depth d + 1. Goldmann, Hastad, and Razborov showed in [10 ..."
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Cited by 37 (0 self)
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We prove that a single threshold gate with arbitrary weights can be simulated by an explicit polynomialsize depth 2 majority circuit. In general we show that a depth d threshold circuit can be simulated uniformly by a majority circuit of depth d + 1. Goldmann, Hastad, and Razborov showed in [10] that a nonuniform simulation exists. Our construction answers two open questions posed in [10]: we give an explicit construction whereas [10] uses a randomized existence argument, and we show that such a simulation is possible even if the depth d grows with the number of variables n (the simulation in [10] gives polynomialsize circuits only when d is constant). 1 A preliminary version of this paper appeared in Proc. 25th ACM STOC (1993), pp. 551560. 2 Laboratory for Computer Science, MIT, Cambridge MA 02139, Email: migo@theory.lcs.mit.edu. This author 's work was done at Royal Institute of Technology in Stockholm, and while visiting the University of Bonn 3 Department of Com...
Amplifying lower bounds by means of selfreducibility
 In IEEE Conference on Computational Complexity
, 2008
"... We observe that many important computational problems in NC 1 share a simple selfreducibility property. We then show that, for any problem A having this selfreducibility property, A has polynomial size TC 0 circuits if and only if it has TC 0 circuits of size n 1+ɛ for every ɛ>0 (counting the numb ..."
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Cited by 13 (4 self)
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We observe that many important computational problems in NC 1 share a simple selfreducibility property. We then show that, for any problem A having this selfreducibility property, A has polynomial size TC 0 circuits if and only if it has TC 0 circuits of size n 1+ɛ for every ɛ>0 (counting the number of wires in a circuit as the size of the circuit). As an example of what this observation yields, consider the Boolean Formula Evaluation problem (BFE), which is complete for NC 1 and has the selfreducibility property. It follows from a lower bound of Impagliazzo, Paturi, and Saks, that BFE requires depth d TC 0 circuits of size n 1+ɛd. If one were able to improve this lower bound to show that there is some constant ɛ>0 such that every TC 0 circuit family recognizing BFE has size n 1+ɛ, then it would follow that TC 0 ̸ = NC 1. We show that proving lower bounds of the form n 1+ɛ is not ruled out by the Natural Proof framework of Razborov and Rudich and hence there is currently no known barrier for separating classes such as ACC 0,TC 0 and NC 1 via existing “natural ” approaches to proving circuit lower bounds. We also show that problems with small uniform constantdepth circuits have algorithms that simultaneously have small space and time bounds. We then make use of known timespace tradeoff lower bounds to show that SAT requires uniform depth d TC 0 and AC 0 [6] circuits of size n 1+c for some constant c depending on d. 1
Applications and Variations of Domination in Graphs
, 2000
"... In a graph G =(V,E), S ⊆ V is a dominating set of G if every vertex is either in S or joined by an edge to some vertex in S. Many different types of domination have been researched extensively. This dissertation explores some new variations and applications of dominating sets. We first introduce the ..."
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Cited by 12 (0 self)
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In a graph G =(V,E), S ⊆ V is a dominating set of G if every vertex is either in S or joined by an edge to some vertex in S. Many different types of domination have been researched extensively. This dissertation explores some new variations and applications of dominating sets. We first introduce the concept of Roman domination. A Roman dominating function is a function f: V →{0, 1, 2} such that every vertex v for which f(v) =0hasa neighbor w with f(w) = 2. This corresponds to a problem in army placement where every region is either defended by its own army or has a neighbor with two armies, in which case one of the two armies can be sent to the undefended region if a conflict breaks out. The weight of a Roman dominating function f is f(V) = � v∈V f(v), and we are interested in finding Roman dominating functions of minimum weight. We explore the graph theoretic, algorithmic, and complexity issues of Roman domination, including algorithms for finding minimum weight Roman dominating functions for trees and grids.
The Complexity of Satisfiability of Small Depth Circuits
 IWPEC
"... We consider the satisfiability problem for circuits of limited size and/or depth. Say that an algorithm solving a Boolean satisfiability problem on n variables is improved iff it takes time O(2 cn) for some constant c < 1, i.e. iff it is exponentially better than a brute force search. We show an imp ..."
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Cited by 9 (4 self)
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We consider the satisfiability problem for circuits of limited size and/or depth. Say that an algorithm solving a Boolean satisfiability problem on n variables is improved iff it takes time O(2 cn) for some constant c < 1, i.e. iff it is exponentially better than a brute force search. We show an improved algorithm for the satisfiability problem for circuits of constant depth and linear size. If improved upper bounds are not possible for a variant where the size is somewhat more than linear or the depth grows, can we provide evidence regarding the hardness of the problem? (note to authors: Did we actually discuss this question in greater depth in the paper? Maybe this should be reworded.) For each d and c, we give a randomized algorithm solving the satisfiability problem for depth d circuits with n variables and at most cn gates in time 2 (1−δ)n where δ ≥ 1/O(c 2d−2 −1 lg 3·2 d−2 −2 c), and the constant in the bigOh depends only on d. The algorithm can be adjusted for use with
Generalization Properties of Modular Networks: Implementing the Parity Function
, 2001
"... The parity function is one of the most used Boolean function for testing learning algorithms because both of its simple definition and its great complexity. Being one of the hardest problems, many different architectures have been constructed to compute parity, essentially by adding neurons in the h ..."
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Cited by 8 (6 self)
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The parity function is one of the most used Boolean function for testing learning algorithms because both of its simple definition and its great complexity. Being one of the hardest problems, many different architectures have been constructed to compute parity, essentially by adding neurons in the hidden layer in order to reduce the number of local minima where gradientdescent learning algorithms could get stuck. We construct a family of modular architectures that implement the parity function in which, every member of the family can be characterized by the fanin max of the network, i.e., the maximum number of connections that a neuron can receive. We analyze the generalization ability of the modular networks first by computing analytically the minimum number of examples needed for perfect generalization and second by numerical simulations. Both results show that the generalization ability of these networks is systematically improved by the degree of modularity of the network. We also analyze the influence of the selection of examples in the emergence of generalization ability, by comparing the learning curves obtained through a random selection of examples to those obtained through examples selected accordingly to a general algorithm we recently proposed.
Multilayer feedforward neural network based on multivalued neurons (MLMVN) and a backpropagation learning algorithm
 SOFT COMPUTING
, 2007
"... A multilayer neural network based on multivalued neurons is considered in the paper. A multivalued neuron (MVN) is based on the principles of multiplevalued threshold logic over the field of the complex numbers. The most important properties of MVN are: the complexvalued weights, inputs and outpu ..."
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Cited by 6 (2 self)
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A multilayer neural network based on multivalued neurons is considered in the paper. A multivalued neuron (MVN) is based on the principles of multiplevalued threshold logic over the field of the complex numbers. The most important properties of MVN are: the complexvalued weights, inputs and output coded by the k th roots of unity and the activation function, which maps the complex plane into the unit circle. MVN learning is reduced to the movement along the unit circle, it is based on a simple linear error correction rule and it does not require a derivative. It is shown that using a traditional architecture of multilayer feedforward neural network (MLF) and the high functionality of the multivalued neuron, it is possible to obtain a new powerful neural network. Its training does not require a derivative of the activation function and its functionality is higher than the functionality of MLF containing the same number of layers and neurons. These advantages of MLMVN are confirmed by testing using parity n, two spirals and "sonar" benchmarks and the MackeyGlass time series prediction.
The Random Adversary: A LowerBound Technique For Randomized Parallel Algorithms
 in Proc. of the 3rd SODA (ACM
, 1997
"... . The randomadversary technique is a general method for proving lower bounds on randomized parallel algorithms. The bounds apply to the number of communication steps, and they apply regardless of the processors' instruction sets, the lengths of messages, etc. This paper introduces the ra ..."
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Cited by 5 (1 self)
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.<F3.82e+05> The randomadversary technique is a general method for proving lower bounds on randomized parallel algorithms. The bounds apply to the number of communication steps, and they apply regardless of the processors' instruction sets, the lengths of messages, etc. This paper introduces the randomadversary technique and shows how it can be used to obtain lower bounds on randomized parallel algorithms for load balancing, compaction, padded sorting, and finding Hamiltonian cycles in random graphs. Using the randomadversary technique, we obtain the first lower bounds for randomized parallel algorithms which are provably faster than their deterministic counterparts (specifically, for load balancing and related problems).<F4.005e+05> Key words.<F3.82e+05> parallel algorithms, parallel computation, PRAM model, randomized parallel algorithms, expected time, lower bounds, load balancing<F4.005e+05> AMS subject classifications.<F3.82e+05> 68Q10, 68Q22, 68Q25<F4.005e+05> PII.<F3.82e+05> ...
Practical LowCost CPL Implementations of Threshold Logic Functions
 in Proc. Great Lakes Symp. VLSI
, 2001
"... This paper gives the rationale for the Complementary PassTransistor Logic (CPL) implementation of threshold gates for the design of complex logic functions. The interesting lowpower properties of CPL circuits and the efficiency with which a broad class of functions can be implemented by threshold ..."
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Cited by 5 (3 self)
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This paper gives the rationale for the Complementary PassTransistor Logic (CPL) implementation of threshold gates for the design of complex logic functions. The interesting lowpower properties of CPL circuits and the efficiency with which a broad class of functions can be implemented by threshold functions make the proposed methodology extremely useful. A number of implementation examples are given which illustrate the feasibility and versatility of the proposed technique and its potential as a lowcost design technique for CMOS technologies. Simulation results confirm our expectations. 1.
Affine Projections of Symmetric Polynomials
 In Proc. 16th Annual IEEE Conference on Computational Complexity
, 2001
"... In this paper we introduce a new model for computing polynomials  a depth 2 circuit with a symmetric gate at the top and plus gates at the bottom, i.e the circuit computes a symmetric function in linear functions  S d m (` 1 ; ` 2 ; :::; ` m ) (S d m is the d'th elementary symmetric polynomial ..."
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Cited by 5 (1 self)
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In this paper we introduce a new model for computing polynomials  a depth 2 circuit with a symmetric gate at the top and plus gates at the bottom, i.e the circuit computes a symmetric function in linear functions  S d m (` 1 ; ` 2 ; :::; ` m ) (S d m is the d'th elementary symmetric polynomial in m variables, and the ` i 's are linear functions). We refer to this model as the symmetric model. This new model is related to standard models of arithmetic circuits, especially to depth 3 circuits. In particular we show that in order to improve the results of [19], i.e to prove superquadratic lower bounds for depth 3 circuits, one must first prove a superlinear lower bound for the symmetric model. We prove two nontrivial linear lower bounds for our model. The first lower bound is for computing the determinant, and the second is for computing the sum of two monomials. The main technical contribution relates the maximal dimension of linear subspaces on which S d m vanishes, and lower bounds to the symmetric model. In particular we show that an answer of the following problem (which is very natural, and of independent interest) will imply lower bounds on symmetric circuits for many polynomials: "What is the maximal dimension of a linear subspace of C m , on which S d m vanishes ?" We give two partial solutions to the problem above, each enables us to prove a different lower bound. Using our techniques we also prove quadratic lower bounds for depth 3 circuits computing the elementary symmetric polynomials of degree n (where 0 < < 1 is a constant), thus extending the result of [19]. These are the best lower bounds known for depth 3 circuits over fields of characteristic zero. 1.