This paper 1 proposes a new method for hardware verification. The basic idea is the application of a retargetable compiler as verification tool. A retargetable compiler is able to compile programs into the machine code of a specified hardware (target). If the program is the complete behavioural specification of the target, the compiler can be used to verify that a properly programmed structure implements the behaviour. Methods, algorithms and applications of an existing retargetable compiler are described. 1 Introduction The correctness of digital systems is relatively neglected by current design systems. It will become even more important, because the systems will become more complex and there will be more critical applications. Simulation, in general, cannot be used for correctness proofs, since the complexity of most systems makes exhaustive simulation impossible. In the past, synthesis and verification have been proposed as means for the design of correct systems. Synthesis has ...

This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans. 1. INTRODUCTION During the recent years, there has been a significant shift in the way complex electronic systems are implemented: various types of embedded processors are being used in many designs. These types include: off-the-shelf DSPs (e.g. TMS320C25 [27]), application-specific instruction set processors (ASIPs, see e.g. [2]), application-specific signal processors (ASSPs) and in-house core processors. The ad...

When developing software for embedded systems, the set of essential tools includes a compiler and an instruction set simulator. Since software and hardware are often designed in parallel, the tools must be easily adaptable to the changing target architecture. For the compiler, its back-end (the code generator) must be retargetable. Abstraction from the target machine is the key to an automated approach. Additionally, abstraction from tool-internal strategies permits the utilization of a unified machine description for all tools. In this chapter, the machine description formalism nML is presented along with the retargetable code generator Cbc and the instruction set simulation environment Sigh/Sim. 1 INTRODUCTION For the realization of retargetable software development tools such as a code generator and an instruction set simulator, several aspects of the potential target machines must be modeled in an abstract manner. These machine models are necessary to formalize the tool's methods...

Mobile and personal communication systems form key market areas for the electronics industry of the nineties. Stringent requirements in terms of flexibility, performance and power dissipation, aredriving the development of integrated circuits into the direction of heterogeneous single-chip solutions. New IC architectures are emerging which contain the core of a powerful programmable processor, complemented with dedicated hardware, memory and interface structures. In this tutorial we will discuss the real-life design of a heterogeneous IC for an industrial telecom application: a reconfigurable mobile terminal for satellite communication. Based on this practical design experience, we will subsequently discuss a methodology for the design of heterogeneous ICs. Design steps that will be addressed include: system specification and refinement, data path and communication synthesis, and code generation for embedded processor cores.

Abstract{In a hardware/software codesign environment compilers are needed that map software components of a partitioned system behavioral description onto aprogrammable processor. Since the processor structure is not static, but can repeatedly change during the design process, the compiler should be retargetable in order to avoid manual compiler adaption for each alternative architecture. A restriction of existing retargetable compilers is that they only generate microcode for the target architecture instead of machine-level code. In this paper we introduce a bootstrapping technique permitting to translate high-level language (HLL) programs into real machine-level code using a retargetable microcode compiler. Retargetability is preserved, permitting to compare di erent architectural alternatives

Integrated circuits in telecommunications and consumer electronics are rapidly evolving towards single chip solutions. New IC architectures are emerging, which combine instruction-set processor cores with customised hardware. This paper describes a highlevel synthesis system for integration of real-time signal processing systems on such processor cores. The compiler supports a flexible architectural model. It can handle certain types of incompletely specified architectures, and offers capabilities for retargetable compilation and architectural exploration. Results for a realistic application from the domain of audio processing indicate the feasibility and power of the presented approach. 1 Introduction The electronic systems industry of the nineties is confronted with the challenge of integrating complex multi-functional systems in silicon. High-volume markets like end-user telecommunications and consumer electronics require cost efficient solutions in the form of applications...

Introduction P. Marwedel 1 New, flexible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and in audio-, video-, and telecommunication-equipment. Essential advantages of these processors include their high flexibility, short design time and (in the case of off-the-shelf processors) full-custom layout quality. Furthermore, they allow an easy implementation of optional product features as well as easy design correction and upgrading. Furthermore, processors are frequently used in cases where the systems must be extremely dependable 1 [32]. In such cases, the re-use of the design of an off-the-shelf processor greatly simplifies dependability analysis. This contrasts with the limitations of application-specific circuits (ASICs): due to their low flexibility, the cost for the desig

This chapter presents a retargetable code generator specialized in the compilation of self-test programs and exploiting new techniques from Constraint Logic Programming (CLP). Firstly, we show how CLP can be exploited to improve the software production process especially for retargetable code generation and test generation. CLP combines the declarative paradigm of logic programming with the efficiency of constraint solving techniques. CLP systems come with built-in mechanisms for solving constraints over various domains. For example, satisfiability checkers support Boolean constraints and IP-solvers support integer domains. Furthermore, CLP makes it easier to solve problems concurrently, e.g. the phase coupling problem during code generation. Secondly, we present a solution for testing embedded processors. Thus we exploit CLP techniques for retargetable code generation to generate self-test programs, given a set of test patterns for each of the register transfer processor components. 1...