Results 1  10
of
152
Power: A FirstClass Architectural Design Constraint
, 2001
"... Power is a design constraint, not only for... ..."
Energy minimization using multiple supply voltages
 In International Symposium on Low Power Electronics and Design
, 1996
"... AbstractWe present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined datapaths. The scheduling problem refers to the assignment of a supply voltage level (selected from a xed and known number of voltage level ..."
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Cited by 141 (5 self)
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AbstractWe present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined datapaths. The scheduling problem refers to the assignment of a supply voltage level (selected from a xed and known number of voltage levels) to each operation in a data ow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, reconvergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using three supply voltage levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single supply voltage level.
Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption
 In Workshop on Complexity Effective Design
, 2000
"... Power and energy are increasingly becoming a limitation for microprocessor design. Modern microprocessors employ a number of techniques to reduce energy consumption. Since modern architectures typically waste activity on speculative execution, prior work has explored microarchitectural mechanisms ..."
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Cited by 69 (1 self)
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Power and energy are increasingly becoming a limitation for microprocessor design. Modern microprocessors employ a number of techniques to reduce energy consumption. Since modern architectures typically waste activity on speculative execution, prior work has explored microarchitectural mechanisms for speculation control. These techniques attempt to adjust the excess speculation in the microarchitecture, but typically seek heuristics that target an "isoperformance" goal  power is reduced, but never at the expense of performance. We argue that this strategy will have limited energy savings because the system performance goal is not clearly articulated to the microarchitecture. We propose that software, including a combination of the operating system and applications, should use a performance mechanism to indicate the desired performance and allow the microarchitecture to then choose between extant methods to achieve that performance while reducing power usage. We demons...
Datapath Scheduling with Multiple Supply Voltages and Level Converters
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1997
"... ..."
Power Aware Microarchitecture Resource Scaling
, 2001
"... In this paper we present a strategy for runtime profiling to optimize the configuration of a microprocessor dynamically so as to save power with minimum performance penalty. The configuration of the processor changes according to the parallelism in the running program. Experiments on some benchmark ..."
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Cited by 43 (1 self)
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In this paper we present a strategy for runtime profiling to optimize the configuration of a microprocessor dynamically so as to save power with minimum performance penalty. The configuration of the processor changes according to the parallelism in the running program. Experiments on some benchmark programs show good savings in total energy consumption; we have observed a decrease of up to 23% in energy/cycle and up to 8% in energy per instruction. Our proposed approach can be used for energyaware computing in either portable applications or in desktop environments where power density is becoming a concern. This approach can also be incorporated in larger power management strategies like ACPI.
HighEfficiency LowVoltage DCDC Conversion for Portable Applications
, 1998
"... Motivated by emerging portable applications that demand ultralowpower hardware to maximize battery runtime, highefficiency lowvoltage DCDC conversion is presented as a key lowpower enabler. Recent innovations in lowpower digital CMOS design have assumed that the supply voltage is a free vari ..."
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Cited by 42 (1 self)
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Motivated by emerging portable applications that demand ultralowpower hardware to maximize battery runtime, highefficiency lowvoltage DCDC conversion is presented as a key lowpower enabler. Recent innovations in lowpower digital CMOS design have assumed that the supply voltage is a free variable and can be set to any arbitrarily low level with little penalty. This thesis introduces and demonstrates an array of DCDC converter design techniques which make this assumption more viable. The primary design challenges to highefficiency lowvoltage DCDC converters are summarized. Design techniques at the power delivery system, individual control system, and circuit levels are described which help meet the stringent requirements imposed by the portable environment. Design equations and closedform expressions for losses are presented. Special design considerations for the key dynamic voltage scaling enabler, called the dynamic DCDC converter are given. The focus throughout is on lowpower portable applications, where small size, low cost, and high energy efficiency are the primary design objectives. The design
Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 40 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
LowPower FPGA Using Predefined DualVdd/DualVt Fabrics
 FPGA'04
, 2004
"... Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt ..."
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Cited by 38 (12 self)
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Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use predefined dualVdd and dualVt fabrics to reduce FPGA power. We design FPGA circuits with dualVdd/dualVt to e#ectively reduce both dynamic power and leakage power, and define dualVdd/dualVt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including powersensitivity based voltage assignment and simulatedannealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the predefined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the predesigned dualVdd layout pattern introduces nonnegligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dualVdd FPGAs. To our best knowledge, it is the first indepth study on applying both dualVdd and dualVt to FPGA considering circuits, fabrics and CAD algorithms.
Minimizing total power by simultaneous Vdd/Vth assignment
 Proc. ASPDAC
, 2003
"... Abstract We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including staticpower limited designs and sub1V pr ..."
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Cited by 37 (3 self)
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Abstract We investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static + dynamic) for the first time. Achievable power reductions under varying conditions are investigated, including staticpower limited designs and sub1V processes. Rules of thumb are developed for optimal Vdd’s and Vth’s to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the total power savings is significantly greater than previously anticipated. We describe the impact of level conversion delays and highlight the tradeoff between power savings and critical path count. I.
On Gate Level Power Optimization Using DualSupply Voltages
 IEEE Trans. on VLSI Systems
, 2001
"... In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technologymapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed ..."
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Cited by 35 (3 self)
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In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technologymapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timingconstrained optimization issues by making full use of slacks. Based on this strategy, the power reduction is translated into the polynomialtimesolvable maximalweightedindependent set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dualsupply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained FM" algorithm to minimize the number of level converters. We have implemented our approach under SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by gate sizing technique based on a standard cell library. Our technique provides the powerdelay tradeoff by specifying different timing constraints in circuits for power optimization.