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24
Symbolic and neural learning algorithms: an experimental comparison
 Machine Learning
, 1991
"... Abstract Despite the fact that many symbolic and neural network (connectionist) learning algorithms address the same problem of learning from classified examples, very little is known regarding their comparative strengths and weaknesses. Experiments comparing the ID3 symbolic learning algorithm with ..."
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Cited by 99 (6 self)
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Abstract Despite the fact that many symbolic and neural network (connectionist) learning algorithms address the same problem of learning from classified examples, very little is known regarding their comparative strengths and weaknesses. Experiments comparing the ID3 symbolic learning algorithm with the perception and backpropagation neural learning algorithms have been performed using five large, realworld data sets. Overall, backpropagation performs slightly better than the other two algorithms in terms of classification accuracy on new examples, but takes much longer to train. Experimental results suggest that backpropagation can work significantly better on data sets containing numerical data. Also analyzed empirically are the effects of (1) the amount of training data, (2) imperfect training examples, and (3) the encoding of the desired outputs. Backpropagation occasionally outperforms the other two systems when given relatively small amounts of training data. It is slightly more accurate than ID3 when examples are noisy or incompletely specified. Finally, backpropagation more effectively utilizes a "distributed " output encoding.
DAGaware AIG rewriting: A fresh look at combinational logic synthesis
 In DAC ’06: Proceedings of the 43rd annual conference on Design automation
, 2006
"... This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rew ..."
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Cited by 76 (32 self)
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This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using AndInverter Graphs (AIGs), the networks of twoinput ANDs and inverters. The optimization works by alternating DAGaware AIG rewriting, which reduces area by sharing common logic without increasing delay, and algebraic AIG balancing, which minimizes delay without increasing area. The new technologyindependent flow is implemented in a publicdomain tool ABC. Experiments on large industrial benchmarks show that the proposed methodology scales to very large designs and is several orders of magnitude faster than SIS and MVSIS while offering comparable or better quality when measured by the quality of the network after mapping. 1
HDL Optimization Using Timed Decision Tables
 in Proceedings of the 33 rd Design Automation Conference
, 1996
"... Systemlevel presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control flow in behavioral HDL descriptions using external Don't Care conditions. The optimiz ..."
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Cited by 14 (6 self)
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Systemlevel presynthesis refers to the optimization of an input HDL description that produces an optimized HDL description suitable for subsequent synthesis tasks. In this paper, we present optimization of control flow in behavioral HDL descriptions using external Don't Care conditions. The optimizations are carried out using a tabular model of system functionality, called Timed Decision Tables or TDTs. TDT based optimization presented here have been implemented in a program called PUMPKIN. Optimization results from several examples show a reduction of 388% in the size of synthesized hardware circuits depending upon the external Don't Care information supplied by the user. 1 Introduction Due to the maturity of optimization and synthesis tools at logic and register transfer level, system specification is increasingly being done at behavioral level using a Hardware Description Language (HDL), such as VHDL and Verilog. Though optimization can be done at all levels of system specificat...
A Heuristic Algorithm to Design ANDOREXOR ThreeLevel Networks
 Proc. Asia and South Pacific Design Automation Conference
, 1998
"... An ANDOREXOR network, where the output EXOR gate has only two inputs, is one of the simplest threelevel architecture. This network realizes an EXOR of two sumofproducts expressions (EXSOP). In this paper, we show an algorithm to simplify EXSOPs for multipleoutput functions. Our objective is t ..."
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Cited by 14 (4 self)
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An ANDOREXOR network, where the output EXOR gate has only two inputs, is one of the simplest threelevel architecture. This network realizes an EXOR of two sumofproducts expressions (EXSOP). In this paper, we show an algorithm to simplify EXSOPs for multipleoutput functions. Our objective is to minimize the number of distinct products in the sumofproducts expressions of EXSOPs. The algorithm uses a divideandconquer strategy. It recursively applies the Shannon decomposition on a function with more than five variables. The algorithm obtains EXSOPs for the fivevariable functions by using an exact minimization program, then combines those EXSOPs to generate EXSOPs for the functions with more variables. We present experimental results for a set of benchmark functions, and show that EXSOPs require many fewer products and literals than sumofproducts expressions. This is evidence that ANDOREXOR is a powerful architecture to realize many practical logic functions. Index Ter...
Factoring and Recognition of ReadOnce Functions using Cographs and Normality
, 2001
"... An approach for factoring general boolean functions was described in [5] which is based on graph partitioning algorithms. In this paper, we presentavery fast algorithm for recognizing and factoring readonce functions which is needed as a dedicated factoring subroutine to handle the lower levels of ..."
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Cited by 12 (0 self)
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An approach for factoring general boolean functions was described in [5] which is based on graph partitioning algorithms. In this paper, we presentavery fast algorithm for recognizing and factoring readonce functions which is needed as a dedicated factoring subroutine to handle the lower levels of that factoring process. The algorithm is based on algorithms for cograph recognition and on checking normality. Our method has been implemented in the SIS environment, and an empirical evaluation is given.
Ternary Decision Diagrams Survey
 Proc. ISMVL '97
, 1997
"... This paper surveys seven types of TDDs: General TDD, SOP TDD, ESOP TDD, AND TDD, prime TDD, EXOR TDD, and Kleene TDD. We give new definitions for SOP TDDs and ESOP TDDs and introduce unifying terminology. After showing some theoremsoncomplexities, we compare the sizes of these TDDs using benchmark f ..."
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Cited by 10 (2 self)
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This paper surveys seven types of TDDs: General TDD, SOP TDD, ESOP TDD, AND TDD, prime TDD, EXOR TDD, and Kleene TDD. We give new definitions for SOP TDDs and ESOP TDDs and introduce unifying terminology. After showing some theoremsoncomplexities, we compare the sizes of these TDDs using benchmark functions. Finally, we review important works on TDDs.
Fast Boolean Matching Under Permutation Using Representative
 in Proc. Asia and South Pacific Design Automation Conf
, 1999
"... This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion Prepresentative. If two functions have the same Prepresentative then th ..."
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Cited by 7 (1 self)
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This paper presents an efficient method to check the equivalence of two Boolean functions under permutation of the variables. The problem is also known as Boolean matching. As a basis of the Boolean matching, we use the notion Prepresentative. If two functions have the same Prepresentative then they match. We develop a breadthfirst search technique to quickly compute the Prepresentative. On an ordinary workstation, on the average, our method requires several microseconds to test the Boolean matching for functions with up to eight variables. This approach is promising for Boolean matching of multiplexorbased fieldprogrammable gate arrays (FPGAs) and for library matching with many large cells. Index TermsBoolean matching, technology mapping, variable permutation, Pequivalence. I. INTRODUCTION Boolean matching is a technique to detect the equivalence of two Boolean functions under permutation of the variables. One of the main application of Boolean matching is in celllibrary...
Efficient Computation of Canonical Form for Boolean Matching in Large Libraries
 in Asia and South Pacific Design Automation Conference
, 2004
"... This paper presents an efficient technique for solving a Boolean matching problem in celllibrary binding, where the number of cells in the library is large. As a basis of the Boolean matching, we use the notion NPrepresentative (NPR); two functions have the same NPR if one can be obtained from the ..."
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Cited by 6 (0 self)
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This paper presents an efficient technique for solving a Boolean matching problem in celllibrary binding, where the number of cells in the library is large. As a basis of the Boolean matching, we use the notion NPrepresentative (NPR); two functions have the same NPR if one can be obtained from the other by a permutation and/or complementation(s) of the variables. By using a table lookup and a treebased breadthfirst search strategy, our method quickly computes NPR for a given function. Boolean matching of the given function against the whole library is determined by checking the presence of its NPR in a hash table, which stores NPRs for all the library functions and their complements. The effectiveness of our method is demonstrated through experimental results, which shows that it is more than two orders of magnitude faster than the HinsbergerKolla's algorithmthe fastest Boolean matching algorithm for large libraries.
An Optimization of ANDOREXOR ThreeLevel Networks
 Proc. Asia and South Pacific Design Automation Conference
, 1997
"... In this paper, we present a design method for ANDOREXOR threelevel networks, where a single twoinput EXOR gate is used. The network realizes an exclusiveOR of two sumofproducts expressions (EXSOP), where the two sumofproducts expressions (SOP) cannot share products. The problem is to minim ..."
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Cited by 5 (3 self)
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In this paper, we present a design method for ANDOREXOR threelevel networks, where a single twoinput EXOR gate is used. The network realizes an exclusiveOR of two sumofproducts expressions (EXSOP), where the two sumofproducts expressions (SOP) cannot share products. The problem is to minimize the total number of product in the two SOPs. Weintroduced the equivalence of logic functions to develop minimization algorithms for EXSOPs with up to fivevariables. We minimized all the representative functions of NPequivalence classes for up to fivevariables and found that fivevariable functions require up to 9 products in minimum EXSOPs. For nvariable functions, minimum EXSOPs require at most 9 1 2 n05 (n 6) products. This upper bound is smaller than 2 n01 , the upper bound for the conventional sumofproducts expressions. Index Terms  Threelevel network, ANDEXOR, logic minimization, spectral method, NPequivalence, equivalence, coordinate representation, complexity. ...
Finite State Systems in Mobile Communications
, 1996
"... Contents Table of Abbreviations x Glossary xi Summary xvi Declaration xvii Acknowledgement xviii 1 Introduction 1 1.1 Digital Communication and Error Control Coding : : : : : : : : : : : : : : : : : 1 1.2 Trellis Coding : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1. ..."
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Cited by 5 (0 self)
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Contents Table of Abbreviations x Glossary xi Summary xvi Declaration xvii Acknowledgement xviii 1 Introduction 1 1.1 Digital Communication and Error Control Coding : : : : : : : : : : : : : : : : : 1 1.2 Trellis Coding : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.3 Performance Estimation for Trellis Codes : : : : : : : : : : : : : : : : : : : : : : 4 1.4 Overview of the Thesis : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 2 System Models and Basics 7 2.1 Trellis Codes : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 2.1.1 Convolutional Codes : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 8 2.1.2 TCM Codes : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 9 2.1.3 CPM Schemes : : : : : : : : : : : : : : : : : : : : :