Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations. Fitting such models requires significantly more simulation samples and solving much larger linear equations. In this paper, we propose a novel projection-based extraction approach, PROBE, to efficiently create quadratic response surface models and capture both interdie and intra-die variations with affordable computation cost. PROBE applies a novel projection scheme to reduce the response surface modeling cost (i.e., both the required number of samples and the linear equation size) and make the modeling problem tractable even for large problem sizes. In addition, a new implicit power iteration algorithm is developed to find the optimal projection space and solve for the unknown model coefficients. Several circuit examples from both digital and analog circuit modeling applications demonstrate that PROBE can generate accurate response surface models while achieving up to 12x speedup compared with the traditional methods. 1.

In this paper, we present a new approach for realistic worst-case analysis of VLSI circuit performances and a novel methodology for circuit performance optimization. Circuit performance measures are modeled as response surfaces of the designable and uncontrollable (noise) parameters. Worst-case analysis proceeds by first computing the worst-case circuit performance value and then determining the worst-case noise parameter values by solving a nonlinear programming problem. A new circuit optimization technique is developed to find an optimal design point at which all of the circuit specifications are met under worst-case conditions. This worst-case design optimization method is formulated as a constrained multi-criteria optimization. The methodologies described in this paper are applied to several VLSI circuits to demonstrate their accuracy and efficiency. Keywords Worst-case analysis, worst-case design optimization. I. Introduction I NEVITABLE fluctuations in the manufacturing proces...

In this paper we propose a RObust Analog Design tool (ROAD) for post-tuning analog/RF circuits. Starting from an initial design derived from hand analysis or analog circuit synthesis based on simplified models, ROAD extracts accurate posynomial performance models via transistor-level simulation and optimizes the circuit by geometric programming. Importantly, ROAD sets up all design constraints to include large-scale process variations to facilitate the tradeoff between yield and performance. A novel convex formulation of the robust design problem is utilized to improve the optimization efficiency and to produce a solution that is superior to other local tuning methods. In addition, a novel projection-based approach for posynomial fitting is used to facilitate scaling to large problem sizes. A new implicit power iteration algorithm is proposed to find the optimal projection space and extract the posynomial coefficients with robust convergence. The efficacy of ROAD is demonstrated on several circuit examples. 1.

Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models parameterized in a high-dimensional process variation space are desired. However, the high parameter dimensionality, imposed by a large number of variation sources encountered in modern technologies, can introduce significant complexion in circuit analysis and may even render performance variability analysis completely intractable. We address the challenge brought by high-dimensional process variations via a new performance-oriented parameter dimension reduction technique. The basic premise behind our approach is that the dimensionality of performance variability is determined not only by the statistical characteristics of the underlying process variables, but also by the structural information imposed by a given design. Using the powerful reduced rank regression (RRR) and its extension as a vehicle for variability modeling, we are able to systematically identify statistically significant reduced parameter sets and compute not only reduced-parameter but also reduced-parameterorder models that are far more efficient than what was possible before. For a variety of interconnect modeling problems, it is shown that the proposed parameter reduction technique can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized interconnect reduced order models. As a general parameter dimension reduction methodology, it is anticipated that the proposed technique is broadly applicable to a variety of statistical circuit modeling problems, thereby offering a useful framework for controlling the complexity of statistical circuit analysis. 1.

In order to design high performance circuits, the relationship between circuit perfor- mance and design parameters must be precisely established. Previously, experimental design techniques have been employed for performance modeling of MOS VLSI devices and circuits. In this paper we describe a new computer-aided methodology for charac- terizing a family of electrical circuits. This methodology is based on multi-stage experi- mental design and prediction through data interpolation. The technique presented here is fully automated and hence helps the designer in efficiently characterizing any circuit response based on full circuit simulations. Through examples, we show the power of this technique in characterizing highly non-linear relationships between circuit performance and the design parameters, in a variety of applications.