Model checkers and other finite-state verification tools allow developers to detect certain kinds of errors automatically. Nevertheless, the transition of this technology from research to practice has been slow. While there are a number of potential causes for reluctance to adopt such formal methods, we believe that a primary cause is that practitioners are unfamiliar with specification processes, notations, and strategies. In a recent paper, we proposed a pattern-based approach to the presentation, codification and reuse of property specifications for finite-state verification. Since then, we have carried out a survey of available specifications, collecting over 500 examples of property specifications. We found that most are instances of our proposed patterns. Furthermore, we have updated our pattern system to accommodate new patterns and variations of existing patterns encountered in this survey. This paper reports the results of the survey and the current status of our pattern system.

For over a decade, researehers m formal methods tried to create formalisms that permit atural specifi'catio of systems ad allow mathematical reasomg about their correctess. The availability of fully-automated reasomg tools eables more omspecialists to use forreal methods efjctively their respotsibility reduces to just specifying the model atd expressing the desired properties. Thus, it is essetial that these properties be represeted m a laguage that is easy to use ad sufficietly expressive.

Model checking has received wide acceptance as a valuable technique in the field of electronic design automation and is currently of growing interest in general systems design. Though the concepts and their application are well understood engineers often have severe problems with the specification process and the underlying notation, i.e., the formulation of properties by means of temporal logic formulae. It becomes even harder when additionally timing constraints have to be specified, such as it is often required in complex reactive or concurrent systems. In this article, we present a novel approach for an advanced visual capture for model checking specification support. Models are This work is sponsored by the German Research Grant (DFG) 1 defined by a sort of concurrent finite state machines and their properties by interactively composing patterns to structured English sentences which are translated to CCTL formulae. The system is based on RAVEN, a model checker with embedded t...

This article describes our approach for the specification and verification of production automation systems with real-time properties. We focus on the graphical MFERT notation and RT-OCL (Real-Time Object Constraint Language) for the specification of state-oriented real-time properties. RT-OCL is an extension of the Object Constraint Language (OCL) that is part of the Unified Modeling Language (UML). We introduce the formal semantics of RT-OCL based on a formal model of UML Class and State Diagrams and provide a mapping to temporal logics. The applicability of our approach is demonstrated by the case study of a manufacturing system with automated guided vehicles.