In this paper, we describe two systolic arrays for computing the edit distance between two genetic sequences using a well-known dynamic programming algorithm. The systolic arrays have been implemented for the Splash 2 programmable logic array, and are intended to be used for database searching. Simulations indicate that that the faster Splash 2 implementation can search a database at a rate of 12 million characters per second, several orders of magnitude faster than implementations of the dynamic programming algorithm on conventional computers. 1 Introduction With the onset of the Human Genome Initiative [1] and constant advances in genetic sequencing technology, genetic sequence data are being generated at an ever increasing rate 1 . As a result, biologists are faced with an influx of new sequences that they would like to classify and study by comparing them to existing databases. The analysis of a newly generated sequence typically involves searching the database for similar sequen...

orting a C compiler to the DISC processor. Justin Diether assisted in the design, hand-layout, and testing of many partially reconfigured circuits. I would also like to thank Paul Graham for his generous assistance and support of our many mutual activities, classes, and projects at BYU. Other graduate students assisting me with this work include Russel Peterson, Mike Rencher, Richard Ross, and Peter Bellows. My advisor, Brad Hutchings, provided essential assistance and encouragement in all of the projects, ideas, and results presented within this work. My decision to complete this degree and write this dissertation was influenced largely by his advice and positive encouragement. Brent Nelson and other faculty members within the Electrical and Computer Engineering department at BYU have provided critical feedback on a wide variety of topics relating to this work. I would also like to acknowledge the insight and assistance of many collaborators researching closely related subjects. For

. Reconfigurable FPGAs provide designers with new implementation approaches for designing high-performance applications. This paper discusses two basic implementation approaches with FPGAs: compiletime reconfiguration and run-time reconfiguration. Compile-time reconfiguration is a static implementation strategy where each application consists of one configuration. Run-time reconfiguration is a dynamic implementation strategy where each application consists of multiple cooperating configurations. This paper introduces these strategies and discusses the implementation approaches for each strategy. Existing applications for each strategy are also discussed. 1 Overview Reconfigurable logic is an emerging branch of computer architecture that seeks to build flexible computing systems that can achieve very high levels of performance --much higher performance than is possible with the highest performance microprocessors, or in many cases, even supercomputers. At the heart of these computing s...

. With the introduction of Splash, Splash 2, PAM, and other reconfigurable computers, a wide variety of algorithms can now be feasibly constructed in hardware. In this paper, we describe the Splash 2 Parallel Genetic Algorithm (SPGA), which is a parallel genetic algorithm for optimizing symmetric traveling salesman problems (TSPs) using Splash 2. Each processor in SPGA consists of four Field Programmable Gate Arrays (FPGAs) and associated memories and was found to perform 6.8 to 10.6 times the speed of equivalent software on a state-of-the-art workstation. Multiple processor SPGA systems, which use up to eight processors, find good TSP solutions much more quickly than single processor and software-based implementations of the genetic algorithm. The four-processor island-parallel SPGA implementation out performed all other SPGA configurations tested. We conclude noting that the described parallel genetic algorithm appears to be a good match for reconfigurable computing machines and that...

. One way to further exploit the reconfigurable resources of SRAM FPGAs and increase functional density is to reconfigure them during system operation. This process is referred to as Run-Time Reconfiguration (RTR). RTR is an approach to system implementation that divides an application or algorithm into time-exclusive operations that are implemented as separate configurations. The Run-Time Reconfiguration Artificial Neural Network (RRANN) is a proof-of-concept system that demonstrates the effectiveness of RTR for implementing neural networks. It implements the popular backpropagation training algorithm as three distinct time-exclusive FPGA configurations: feed-forward, backpropagation and update. System operation consists of sequencing through these three reconfigurations at run-time, one configuration at a time. RRANN has been fully implemented with Xilinx FPGAs, tested and shown to increase the functional density of a network up to 500% when compared to FPGA-based implementations tha...

Multi-FPGA systems have tremendous potential, providing a high-performance computing substrate for many different applications. One of the keys to achieving this potential is a complete, automatic mapping solution that creates high-quality mappings in the shortest possible time. In this paper we consider one step in this process, the assignment of inter-FPGA signals to specific I/O pins on the FPGAs in a multi-FPGA system. We show that this problem can neither be handled by pin assignment methods developed for other applications nor standard routing algorithms. Although current mapping systems ignore this issue, we show that an intelligent pin assignment method can achieve both quality and mapping speed improvements over random approaches. Intelligent pin assignment methods already exist for multi-FPGA systems, but are restricted to topologies where logic-bearing FPGAs cannot be directly connected. In this paper we provide three new algorithms for the pin assignment of multi...

Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set while generating code for a given application. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. 1. Can application performance be improved if the compiler had the freedom to pick the instruction set on a per application basis? 2. Can we build cost-effective processors that provide the ability to efficiently emulate compiler determined instruction sets and yet are not application specific? 3. Given that the desired processor capabilities are feasible, can the compiler determine an optimal set of instructions for a given application and generate code that can effectively exploit the processor capabilities? In this thesis, we provide sufficient evidence to answer these questions in the affirmative. Through a combination of architectural innovations and novel compilation techniques, this dissertation demonstrates that it is possible to attain significant improvement in performance, up to an order of magnitude in some cases, on general purpose and multimedia applications over comparable fixed ISA processors. We propose classes of microprocessors that allow application programs to add and subtract functional units yielding a dynamically varying instruction set interface to the running application without compromising current compatibility model. First half of this dissertation describes this novel class of architectures, focusing on a specific subclass called Adaptive Explicitly Parallel Instruction Computing (AEPIC) architectures...

FPGA systems outperform many ASIC and super computer systems through effective use of the reconfigurable resource. Reusing design effort across different applications requires a standard, flexible software environment. Driving FPGA systems from ANSI C is possible using lcc (an ANSI C compiler) targeted at an FPGA system and dasm (a retargetable, flexible assembler) . The compiler supports custom hardware capabilities of FPGA systems, as well as all constructs of C. The assembler reads instruction definitions at assemble time, allowing the user to add new custom hardware functions which dasm can assemble correctly to an instruction stream the hardware executes. A source code debugger has been implemented for this system. 1 Introduction FPGAs are capable of achieving high performance on many application-specific tasks. In many cases performance achievable with FPGAs on certain applications exceeds comparable ASIC designs or even super computers[2, 7]. One approach used in obtaining this...

The addition of programmable logic to RISC machines has the potential of exploiting the inherent parallelism of hardware to speedup an application. In this paper, we study the effect of adding a programmable accelerator to DLX, a RISC prototype. We build this model and parameterize the communication overhead between the processor and programmable unit and logic/routing delays inside the programmable unit. We use simulation to evaluate the performance of this model, parameterized by communication overhead and logic delays, by comparing it with the baseline DLX architecture on some sample problems. Our methodology is useful in studying the relative importance of the parameters and in projecting the performance of the system, if the programmable logic were to be implemented inside the processor. Key Words: Programmable Logic, FPGA, HardwareSoftware Co-design, RISC. 1 Introduction The RISC philosophy is to provide primitives not solutions to the compiler writer. By providing simple prim...

As computing platforms gain greater and greater computational power, new applications that previously were unthinkable are being developed. One such application is the ability to automatically identify objects in radar images called Automatic Target Recognition (ATR). This thesis specifically deals with ATR algorithms developed to search for objects in Synthetic Aperture Radar (SAR) images. The algorithms require more computational power than is currently available in any platforms. These algorithms were used as a tool to compare two reconfigurable hardware platforms because of these high computational requirements. Two implementations of ATR for SAR have been developed to compare Teramac and Splash-2 Field Programmable Gate Array (FPGA) based platforms. This comparison shows Teramac's strength as an exploratory platform and Splash-2's strength as an implementation platform for linear systolic array designs. COMMITTEE APPROVAL: Brad L. Hutchings, Committee Chairman James K. Archibald, ...