Compressionless Routing (CR) is a new adaptive routing framework which provides a unified framework for efficient deadlock-free adaptive routing and fault-tolerance. CR exploits the tight-coupling between wormhole routers for flow control to detect and recover from potential deadlock situations. Fault-tolerant Compressionless Routing (FCR) extends CR to support end-toend fault-tolerant delivery. Detailed routing algorithms, implementation complexity, and performance simulation results for CR and FCR are presented. These results show that the hardware for CR and FCR networks is modest. Further, CR and FCR networks can achieve superior performance to alternatives such as dimension-order routing. Compressionless Routing has several key advantages: deadlock-free adaptive routing in toroidal networks with no virtual channels, simple router designs, order-preserving message transmission, applicability to a wide variety of network topologies, and elimination of the need for buffer allocation messages. Fault-tolerant Compressionless Routing has several additional advantages: data integrity in the presence of transient faults (nonstop fault-tolerance), permanent faults tolerance, and elimination of the need for software buffering and retry for reliability. The advantages of CR and FCR not only simplify hardware support for adaptive routing and fault-tolerance, they also can simplify software communication layers.

. Arctic is a 4x4 packet routing chip being developed for the *T multiprocessor. Arctic can be used to implement a variety of staged networks and will be used to implement a fat tree network for *T. Arctic meets the requirements of *T and of a wide class of systems. This paper discusses the key features of Arctic. These include its buffering scheme which enables very high utilization of network links and its test and control system which provides error detection, limited error handling, and in-circuit testability. 1 Introduction Arctic is a four input four output packet router implemented on a Motorola H4CP gate array chip. Arctic has all the features necessary for use in a commercial multiboard multiprocessor such as *T [7, 8, 1]. It has high bandwidth (200 MBytes/sec/port), two priority levels, packet sizes up to 96 bytes, and extensive error detection; it has limited error handling, keeps statistics, can directly drive long PC traces, and provides significant testing suppor...

This paper describes the interconnection network for Monsoon, a parallel processing dataflow computer. This network provides reliable, high bandwidth, low latency communication between the nodes of Monsoon. The major components of this network are two gate arrays: PaRC and the DLC. PaRC (Packet switched Routing Chip) is a CMOS gate array that implements a 4x4 packet routing switch that provides a high raw bandwidth (800Mbits/sec) to each port. PaRC is designed so that much of this bandwidth can be utilized. The DLC (Data Link Chip) is a high speed ECL gate array that reliably transfers data between boards. 1 Introduction Monsoon [5],[6] is a dataflow multiprocessor currently being built by MIT and Motorola. There are two types of nodes in Monsoon: highly pipelined processing elements and memory modules that support I-structure storage. The nodes communicate solely by passing fixed sized messages known as tokens; this is done using a packet switched interconnection network. A node use...

. The Arctic Switch Fabric technology is a scalable network technology based on the Arctic router chip. Switch Fabrics are fat tree networks that are capable of providing high performance even under a heavy load of large (96 byte) packets. They have a number of diagnostic features that make them well suited for experimental computer systems. Switch Fabrics will be used in the StarT-Jr, StarT-Voyager, and Xolas computer systems at MIT. This paper describes the overall characteristics of Switch Fabrics and describes the three layers of Fabric components. These are the 16-leaf network, the four-leaf board, and the Arctic router chip. 1 Introduction The Arctic Switch Fabric technology is a scalable network technology based on the Arctic router chip [2]. An Arctic Switch Fabric is a fat tree network which supports 150 MB/sec bandwidth in each direction at each endpoint and has a bisection bandwidth equal to 150 MB/sec times the number of endpoints divided by two. A Switch Fabric is current...

Simple hardware mechanisms can speed up interprocessor communication dramatically for off-the-shelf processors. This dissertation addresses the problem of efficient interprocessor communication using a framework consisting of a user-level network interface and fast userlevel interrupts. The network interface allows fast receiving, processing, and sending of messages, while fast interrupts reduce the cost of detecting communication events such as a message arrival or an access to non-local memory. The network interface can provide a major performance boost with no modifications to the processor itself. Our network interface (NI) is user level rather than kernel level, allowing messages to be handled without operating-system interactions. The NI is registeroriented rather than FIFO oriented, allowing the various elements of a message to be read and written in an arbitrary order. The NI provides enhancements for common operations such as dispatching on, replying to,and forwarding of messa...

This report describes research done at the Laboratory for Computer Science of the Massachusetts Institute of Technology. Funding for the Laboratory is provided in part by the Advanced Research Projects Agency of the Department of Defense under the Office of Naval Research contract N00014-89-J-1988. Contents 1 Introduction 2 2 Programmer's View 3