This dissertation presents a set of techniques for representing the high-level behavior of a digital subsystem as a collection of nondeterministic finite automata, NFA. Desired behavioral and implementation dynamics: dependencies, repetition, bounded resources, sequential character, and control state, can also be similarly modeled. All possible system execution sequences, obeying imposed constraints, are encapsulated in a composed NFA. Technology similar to that used in symbolic model checking enables implicit exploration and extraction of best-possible execution sequences. This provides a very general, systematic procedure to perform exact high-level synthesis of cyclic, control-dominated behaviors constrained by arbitrary sequential constraints. This dissertation further demonstrates that these techniques are scalable to practical problem sizes and complexities. Exact scheduling solutions are constructed for a variety of academic and industrial problems, including a pipelined RISC processor. The ability to represent and schedule sequential models with hundreds of tasks and one-half million control cases substantially raises the bar as to what is believed possible for exact scheduling models. Keywords: Scheduling; Binary Decision Diagrams; High-Level Synthesis; Nondeterminism; Automata; Symbolic Model.

This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfills the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches.

Conventionally, when a synchronous sequential circuit is synthesized, storage units are implemented in either edgetriggered flip-flops or level-sensitive latches, but not both, depending on the clocking scheme (one- or two-phase) used. We propose that, in the former case, some of the flip-flops can be replaced with latches. Since a latch is generally smaller, faster and less power-consuming than a flip-flop, this replacement leads to improvements in circuit area, performance and power consumption. Whether a flip-flop can be replaced with a latch depends on not only its structural context but also its temporal behavior. In this paper, we first present conditions under which a straightforward replacement can be made; then, we propose two retiming-based transformations that increase the number of replaceable flip-flops. We have implemented the proposed idea in a software called FF2Latch. Experimental results on a set of control-dominated circuits from the high-level synthesis benchmark set [1] show that a large number of the flipflops can be replaced with latches. Up to 22% reduction in the circuit area and up to 73% reduction in the power consumption have been achieved.

Behavioral-Level Guidance Using Property-Based Design Lisa Marie Guerra Doctor of Philosophy in Engineering --- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Jan M. Rabaey, Chair The growing importance of optimization, short time to market windows, and exponentially growing design complexity are just a few of the factors shaping the state-of-the-art synthesis process. In particular, optimization at the early stages of design is crucial --- at the system and behavioral levels, orders of magnitude performance improvement in key design metrics such as throughput, power, and area can be attained. This requires, however, strategic and coordinated application of design techniques best suited for a target design. The problem, however, is the number of options currently available is overwhelming, and as a result, design exploration is often conducted in a qualitative, ad-hoc manner.

A new parallel-in-parallel-out bit-level pipelined multiplier is presented to perform multiplication in GF(2 m ). The existing designs use m 2 identical cells each having 7 latches and have a system latency of 3m. We start with the Dependence Graph (DG) of the algorithm and pipleine it to achieve a critical path equal to the delay of a 2-input AND and XOR gate. The critical path in the proposed design is the same as in previous designs. The number of latches required per cell has however, been reduced from 7 to 3. This results in considerable hardware savings and the system latency is also reduced form the present 3m to m+1 in the proposed design. A chip has been designed using Magic to implement the proposed multiplier. Introduction In recent years, Finite Fields have received a lot of attention because of their application in error control coding [1] [2]. They have also been used in digital signal processing, pseudorandom number generation, encryption and decryption protocols in...

Implementation platform selection is an important component of hardware--software codesign process which selects, for a given computation, the most suitable implementation platform. In this paper, we study the complementary component of hardware--software codesign, algorithm selection. Given a set of specifications for the targeted application, algorithm selection refers to choosing the most suitable completely specified computational structure for a given set of design goals and constraints, among several functionally equivalent alternatives. While implementation platform selection has been recently widely and vigorously studied, the algorithm selection problem has not been studied in computer-aided design domain until now.

Abstract–Scan design has a performance penalty that affects the critical path delay by an added fanout at the origin and a multiplexer at the destination. This problem is outlined in a recent paper [10], which also proposes a solution. The purpose of the present work is to provide a retiming solution. Retiming of a synchronous sequential circuit is a transformation that moves flipflops through combinational logic without altering the function. We move the destination flip-flop of a critical path backward through its scan multiplexer. This splits the flip-flop into three, one on each input of the multiplexer. First of these is the “original flip-flop ” in the normal data path. The second, called “shadow flip-flop”, appears only in the scan path. The third flip-flops from all critical paths are replaced by a single flip-flop that generates a delayed scan enable signal for controlling all retimed multiplexers. We further show how the fanout delay at the origin of a critical path can be eliminated by additional retiming. The use of the formally proven retiming transformations preserve both the function of the circuit and its scan operation without any change. The retimed scan, therefore, can test DC as well as delay faults. Benchmark results show further timing improvement and reduced hardware overhead compared to previously reported results [10]. 1