We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal trade-o s among competing performance measures such aspower, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal trade-o curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a

A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach. Keywords--- Layout, Analog Design, Constraint-Driven Layout. I. Introduction The layout of analog circuits is intrinsically more difficult than the d...

In this paper we present a technique for constraint allocation in analog system synthesis. Constraint allocation is the process of assigning constraint budgets to the subsystems so that the user asserted system level constraints are satisfied. Our approach is based on the formulation of the constraint allocation problem as a constraint satisfaction problem (CSP) and solving it. The solution method employed uses interval techniques to check for the satisfiability of the CSP. The generation of the exact set of solutions is done by an interval reduction and instantiation mechanism. We also discuss the constraint allocation mechanism in the context of a mixed-signal synthesis system. Finally, we present a design example to validate the constraint allocation technique. 1 Introduction Constraint allocation is an important step in analog system synthesis. Given the system level constraints, constraint allocation refers to the process of assigning constraint budgets to each of the components...

We describe a top-down, constraint-driven design methodology for Analog Circuits. We delineate some of the tools that support it. Finally, we conclude with examples to better illustrate the methodology and its integration with the tool set.