...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

In this paper, work is described on the fabrication of highly uniform 8 8 arrays of GaAs--AlGaAs vertical-cavity surface-emitting lasers (VCSEL's). Oxide-confined VCSEL arrays show an average threshold current of 0.74 0.02 mA, an average output power of 2.05 0.03 mW at 8 mA and an average power conversion efficiency of 14.3%. Their wavelength is measured to be 967 0.35 nm over the array. In addition, we describe the alignment and integration of these device arrays with arrays of refractive microlenses to allow beam shaping typically required in system applications.

The list of applications requiring high performance computing resources is constantly growing. The cost of inter-processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. This paper considers the feasibility of a commodity processorbased system which uses a free-space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible.