Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications. However, in the worst case, a high latency hardware floating-point divider can contribute an additional 0.50 CPI to a system executing SPECfp92 applications. This paper presents the system performance impact of floating-point division latency for varying instruction issue rates. It also examines the performance implications of shared multiplication hardware, shared square root, on-the-fly rounding and conversion, and fused functional units. Using a system level study as a basis, it is shown how typical floating-point applications can guide the designer in making implementation decisions and trade-offs.

For specified program behavior and clocking overhead, there is an optimum cycle time. This can be improved somewhat by using wave pipelining, but program unpredictability ultimately limits performance by restricting both cycle time and instruction level parallelism. Algorithm and application implementation should be based on understanding of program behavior, CAD tools, and technology. System on a chip can be realized as die potential increases. This system die then consists of collecting a variety of functional implementations and chip. These include core processor, floating point unit signal processors, cache, message compression and encryption, etc. Functional implementations involve selecting particular algorithms so that total application execution time is minimized under the constraints of fixed die area. Underlying all improvements in processor architecture are fundamental notions of the optimum use of time and space. In silicon CMOS technologies, the notion of optimum cost-- p...