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An Operational Semantics of a Simulator Algorithm
 International Institute for Software Technology, United Nations University
, 2000
"... The semantics of a hardware description language is usually given informally in terms of how a simulator should behave. We give an operational semantics of simple version of Verilog hardware description language. We also outline some techniques of possible formal reasoning based on the operational s ..."
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Cited by 11 (3 self)
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The semantics of a hardware description language is usually given informally in terms of how a simulator should behave. We give an operational semantics of simple version of Verilog hardware description language. We also outline some techniques of possible formal reasoning based on the operational semantics.
Towards an Operational Semantics of Verilog
, 1998
"... We give an operational semantics of simple version of Verilog hardware description language. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniq ..."
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Cited by 6 (0 self)
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We give an operational semantics of simple version of Verilog hardware description language. Gerardo Schneider is a fellow of UNU/IIST, on leave from Catholic University of Pelotas, Brazil, where he is a lecturer. Xu Qiwen is a Research Fellow of UNU/IIST. His research interest is in Formal Techniques of Programming, including Theory for Concurrency and Real Time, Verification and Design Calculi. Email: qxu@iist.unu.edu Copyright c fl 1998 by UNU/IIST, Gerardo Schneider and Xu Qiwen Contents i Contents 1 Introduction 1 2 A Subset of Verilog and its Operational Semantics 1 2.1 Procedural Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 Event control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Continuous Assignment . . ....
A Complete Fragment of HigherOrder Duration µCalculus
 LNCS 1974, SpringerVerlag
, 2000
"... The paper presents an extension HDC of Higherorder Duration Calculus (HDC,[ZGZ99]) by a polyadic least fixed point () operator and a class of nonlogical symbols with a finite variability restriction on their interpretations, which classifies these symbols as intermediate between rigid symbols and ..."
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Cited by 5 (3 self)
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The paper presents an extension HDC of Higherorder Duration Calculus (HDC,[ZGZ99]) by a polyadic least fixed point () operator and a class of nonlogical symbols with a finite variability restriction on their interpretations, which classifies these symbols as intermediate between rigid symbols and flexible symbols as known in DC. The operator and the new kind of symbols enable straightforward specification of recursion and data manipulation by HDC. The paper contains a completeness theorem about an extension of the proof system for HDC by axioms about and symbols of finite variability for a class of simple HDC formulas, which extends the original class of simple DC formulas introduced in [DW94]. The new class extends the original one by allowing subformulas of finite variability and existential quantification over both individual and program variables. The completeness theorem is proved by the method of local elimination of the extending operator , which was earlier used for a simil...
Probabilistic Interval Temporal Logic and Duration Calculus with Infinite Intervals: Complete Proof Systems
 Logical Methods in Computer Science
"... Abstract. The paper presents probabilistic extensions of interval temporal logic (ITL) and duration calculus (DC) with infinite intervals and complete Hilbertstyle proof systems for them. The completeness results are a strong completeness theorem for the system of probabilistic ITL with respect to ..."
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Cited by 1 (1 self)
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Abstract. The paper presents probabilistic extensions of interval temporal logic (ITL) and duration calculus (DC) with infinite intervals and complete Hilbertstyle proof systems for them. The completeness results are a strong completeness theorem for the system of probabilistic ITL with respect to an abstract semantics and a relative completeness theorem for the system of probabilistic DC with respect to realtime semantics. The proposed systems subsume probabilistic realtime DC as known from the literature. A correspondence between the proposed systems and a system of probabilistic interval temporal logic with finite intervals and expanding modalities is established too.
Software Technology Reasoning about QoS Contracts in the Probabilistic Duration Calculus
, 2007
"... Centre of the United Nations University (UNU). It is based in Macao, and was founded in 1991. It started operations in July 1992. UNUIIST is jointly funded by the government of Macao and the governments of the People’s Republic of China and Portugal through a contribution to the UNU Endowment Fund. ..."
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Centre of the United Nations University (UNU). It is based in Macao, and was founded in 1991. It started operations in July 1992. UNUIIST is jointly funded by the government of Macao and the governments of the People’s Republic of China and Portugal through a contribution to the UNU Endowment Fund. As well as providing twothirds of the endowment fund, the Macao authorities also supply UNUIIST with its office premises and furniture and subsidise fellow accommodation. The mission of UNUIIST is to assist developing countries in the application and development of software technology. UNUIIST contributes through its programmatic activities: 1. Advanced development projects, in which software techniques supported by tools are applied, 2. Research projects, in which new techniques for software development are investigated, 3. Curriculum development projects, in which courses of software technology for universities in developing countries are developed, 4. University development projects, which complement the curriculum development projects by aiming to strengthen all aspects of computer science teaching in universities in developing countries, 5. Schools and Courses, which typically teach advanced software development techniques, 6. Events, in which conferences and workshops are organised or supported by UNUIIST, and
Formalising VERILOG: Operational Semantics and Bisimulation
, 2001
"... This report presents an operational semantics for the VERILOG processes using the notations proposed by Plotkin. An advantage of the availability of an operational semantics is the increased understanding and the possibility of formal reasoning that this brings. We define a bisimulation to identify ..."
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This report presents an operational semantics for the VERILOG processes using the notations proposed by Plotkin. An advantage of the availability of an operational semantics is the increased understanding and the possibility of formal reasoning that this brings. We define a bisimulation to identify processes of the same behaviour, aiming at providing a sound basis for derivation of the algebraic laws for the VERILOG Hardware Description Language.
Correct Hardware Compilation with Verilog HDL
"... . Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Durat ..."
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. Hardware description languages usually include features which do not have a direct hardware interpretation. Recently, synthesis algorithms allowing some of these features to be compiled into circuits have been developed and implemented. Using a formal semantics of Verilog based on Relational Duration Calculus, we give a number of algebraic laws which Verilog programs obey, using which, we then prove the correctness of a hardware compilation procedure. 1
A Verilog Specification of STARI
, 1998
"... Verilog is a Hardware Description Language used for the design and description of hardware in a behavioral and structural way. It has some interesting features like concurrency, synchronism, shared variables, nonblocking assignments (scheduled assignments), timing controls, infinite computations, z ..."
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Verilog is a Hardware Description Language used for the design and description of hardware in a behavioral and structural way. It has some interesting features like concurrency, synchronism, shared variables, nonblocking assignments (scheduled assignments), timing controls, infinite computations, zerotime computations, etc., that makes it an interesting language to study. This report explains some features of Verilog in an informal way through small examples and presents the Verilog code of STARI as a main application. Copyright c fl 1998 by UNU/IIST, Pablo Giambiagi and Gerardo Schneider Contents i Contents 1