In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multi-phase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to clock skew management problems. In this paper, we present TSEL, the first energy-recovering logic family that operates with a single-phase clocking scheme. TSEL outperforms previous energy-recovering logic families in terms of energy efficiency and operating speed. In HSPICE simulations with a standard 0.5¯m technology from MOSIS, pipelined carry-lookahead adders in TSEL function correctly for operating frequencies exceeding 280MHz. For operating frequencies above 80MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energyrecovering l...

Adiabatic circuits offer a promising alternative to conventional circuitry for low energy design. Their operation is nevertheless subject to fundamental energy-speed trade-offs, just like any other physical realization of boolean logic. Thus, adiabatic circuits with very low energy consumption at low frequencies fail to function at high operating frequencies. Conversely, high-speed adiabatic circuits tend to be dissipative at low clock rates. This paper describes SCAL, a single-phase source-coupled adiabatic logic family that operates efficiently across a wide range of operating frequencies. In layout-based simulations with 0.5m CMOS process parameters, pipelined carry-lookahead adders developed in our logic function correctly from 10MHz up to 280MHz. Our SCAL adders are less dissipative than corresponding designs in alternative adiabatic families that remain functional across the same frequency range. Moreover, they are about as dissipative as other adiabatic circuits that are gear...

This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5 m standard CMOS process with an active area of 0.470mm . Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.

Recently discovered high-speed single-phase adiabatic logic families require efficient sinusoidal power-clock generators. In this paper we propose a low-power resonant clock-generator built around a zero-voltage switching push-pull power conversion topology. We describe a novel energy-efficient control circuit for this power converter, based on an asynchronous CMOS state machine. We also describe an integrated sub-micron CMOS implementation of our power converter and control circuits. Simulation results show efficiencies in excess of 90%, even under suboptimal tuning conditions, for frequencies over 200MHz. We have fabricated our clock generator in a 0.5   m standard CMOS process. Using an external surface-mount inductor as the resonant element, we have verified the correct operation of the clock generator when driving a singlephase adiabatic 8-bit multiplier.

In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generatox Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitry of 9lpJ per multiplication at IOOMHz. The chip has been fabricated in a 0.5pm standard CMOS process with an active area of 0.47mm2. Correct chip operation has been validated for operating frequencies up to I~OMHZ, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions. 1

Abstract — A resonant adiabatic mixed-signal VLSI array delivers 480 GMACS (10 9 multiply-and-accumulates per second) throughput for every mW of power, a 25-fold improvement over the energy efficiency obtained when resonant clock generator and line drivers are replaced with static CMOS drivers. Losses in resonant clock generation are minimized by activating switches between LC tank and DC supply with a periodic pulse signal, and by minimizing the variability of the capacitive load to maintain resonance. We show that minimum energy is attained for relatively wide pulse width, and that typical load distribution in template-based charge-mode computation implies almost constant capacitive load. The resonantly driven 256×512 array of 3-T chargeconserving multiply-accumulate cells is embedded in a template matching processor for image classification and validated on a face detection task. Index Terms — Adiabatic low-power techniques, resonant clock supply, computational memory, pattern recognition. I.

This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe properties of clocked signals. Next two types of power-clocked CMOS circuit constructions are introduced and analyzed in detail. Since the adiabatic switching requires slow-ramping of the power-clock, a clocked transmission gate and a four-stage clocked NP-domino circuit are presented, which receive trapezoidal and sinusoidal power-clocks, respectively. PSPICE simulations demonstrate the correct operation and energy-saving advantage of the proposed circuits.

Abstract — Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV 2 rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these so-called energyrecovering systems approach charge recycling from a more practical angle, achieving operating frequencies in the hundreds of MHz with relatively low overhead. Among other energy recovering designs, researchers in the field have demonstrated microcontrollers, standard-cell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multi-GHz clock networks. In this tutorial, we will present an overview of the field, focusing on the most promising charge recovering design techniques for ASICs that are close to integration into the field. I.

Abstract—In this paper, we present Boost Logic, a chargerecovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post-layout simulations of 16-bit multipliers with a 0.13- m CMOS process at 1 GHz, a Boost Logic implementation achieves 5 times higher energy efficiency than its minimum-energy pipelined, voltage-scaled, static CMOS counterpart at the expense of 3 times longer latency. In a fully integrated test chip implemented using a 0.13- m bulk silicon process and on-chip inductors, chains of Boost Logic gates operate at clock frequencies up to 1.3 GHz with a 1.5-V supply. When resonating at 850 MHz with a 1.2-V supply, the Boost Logic test chip achieves 60 % charge-recovery. Index Terms—Adiabatic, charge-recovery, energy recovery, resonant systems.

Abstract. The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks (SDA) especially against differential power analysis (DPA) attacks. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with DPA-resistant logic styles proposed so far. 1