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23
True SinglePhase EnergyRecovering Logic for LowPower, HighSpeed VLSI
 In Proceedings of International Symposium on LowPower Electronics and Design
, 1998
"... In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multiphase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distrib ..."
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Cited by 14 (4 self)
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In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multiphase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for highspeed design due to clock skew management problems. In this paper, we present TSEL, the first energyrecovering logic family that operates with a singlephase clocking scheme. TSEL outperforms previous energyrecovering logic families in terms of energy efficiency and operating speed. In HSPICE simulations with a standard 0.5¯m technology from MOSIS, pipelined carrylookahead adders in TSEL function correctly for operating frequencies exceeding 280MHz. For operating frequencies above 80MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energyrecovering l...
SinglePhase SourceCoupled Adiabatic Logic
 in Proceedings of International Symposium on LowPower Electronics and Design
, 1999
"... Adiabatic circuits offer a promising alternative to conventional circuitry for low energy design. Their operation is nevertheless subject to fundamental energyspeed tradeoffs, just like any other physical realization of boolean logic. Thus, adiabatic circuits with very low energy consumption at l ..."
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Adiabatic circuits offer a promising alternative to conventional circuitry for low energy design. Their operation is nevertheless subject to fundamental energyspeed tradeoffs, just like any other physical realization of boolean logic. Thus, adiabatic circuits with very low energy consumption at low frequencies fail to function at high operating frequencies. Conversely, highspeed adiabatic circuits tend to be dissipative at low clock rates. This paper describes SCAL, a singlephase sourcecoupled adiabatic logic family that operates efficiently across a wide range of operating frequencies. In layoutbased simulations with 0.5m CMOS process parameters, pipelined carrylookahead adders developed in our logic function correctly from 10MHz up to 280MHz. Our SCAL adders are less dissipative than corresponding designs in alternative adiabatic families that remain functional across the same frequency range. Moreover, they are about as dissipative as other adiabatic circuits that are gear...
A True SinglePhase 8bit Adiabatic Multiplier
, 2001
"... This paper presents the design and evaluation of an 8bit adiabatic multiplier. Both the multiplier core and its builtin selftest logic have been designed using a true singlephase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal powerclock waveform that is g ..."
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Cited by 9 (3 self)
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This paper presents the design and evaluation of an 8bit adiabatic multiplier. Both the multiplier core and its builtin selftest logic have been designed using a true singlephase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal powerclock waveform that is generated onchip. In HSPICE simulations with postlayout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and selftest circuitry approaches 130pJ per operation at 200MHz. Our 11,854transistor chip has been fabricated in a 0.5 m standard CMOS process with an active area of 0.470mm . Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.
Implementing and Evaluating Adiabatic Arithmetic Units
 In IEEE 1996 Custom Integrated Circuit Conference
, 1996
"... In recent years, several adiabatic logic architectures have been proposed for lowpower VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of low ..."
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Cited by 7 (3 self)
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In recent years, several adiabatic logic architectures have been proposed for lowpower VLSI design. However, no work has been presented describing the implementation and evaluation of nontrivial adiabatic circuits. We have evaluated a specific adiabatic architecture and used it in the design of lowpower arithmetic units. We investigated implementation issues specific to adiabatic system development and performed a systematic comparison of our designs with corresponding CMOS circuits. In this paper we describe our adiabatic designs, discuss implementation issues at the logic and architectural level, and report our empirical findings. 1. Introduction Lowpower circuit design methodologies based on the thermodynamic principle of adiabatic changes have received considerable attention in recent years. Adiabatic circuits achieve low energy consumption by maintaining small potential differences across their devices while they are conducting and by allowing the energy stored in their capac...
nMOS reversible energy recovery logic for ultralowenergy applications," will be published in
 IEEE Journal of SolidState Circuits
, 2000
"... Abstract—We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrap ..."
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Abstract—We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at lowspeed operation. We evaluated a test chip implemented with 0.8 m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at dd = 3 5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at dd = 0 9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption. Index Terms—6phase clocked power generator, adiabatic circuit, bootstrapped switch, energy consumption, nMOS reversible energy recovery logic. I.
Design, verification, and test of a true singlephase 8bit adiabatic multiplier
 In Proceedings of 19th Conference on Advanced Research in VLSI
, 2001
"... In this paper, we present the design and experimental evaluation of an 8bit adiabatic multiplier with builtin selftest (BIST) logic and an internal singlephase sinusoidal powerclock generatox Both the multiplier and the BIST have been designed in SCALD, a true singlephase adiabatic logic fami ..."
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In this paper, we present the design and experimental evaluation of an 8bit adiabatic multiplier with builtin selftest (BIST) logic and an internal singlephase sinusoidal powerclock generatox Both the multiplier and the BIST have been designed in SCALD, a true singlephase adiabatic logic family. In HSPICE simulations with postlayout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitry of 9lpJ per multiplication at IOOMHz. The chip has been fabricated in a 0.5pm standard CMOS process with an active area of 0.47mm2. Correct chip operation has been validated for operating frequencies up to I~OMHZ, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions. 1
Energy Recovery Design for LowPower ASICs
"... Abstract — Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV 2 rate for CMOS switching power. Early engineering ..."
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Cited by 4 (0 self)
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Abstract — Three decades ago, theoretical physicists suggested that the controlled recovery of charges could result in electronic circuitry whose power dissipation approaches thermodynamic limits, growing at a significantly slower pace than the fCV 2 rate for CMOS switching power. Early engineering research in this field, which became generally known as adiabatic computing, focused on the asymptotic energetics of computation, exploring VLSI designs that use reversible logic and adiabatic switching to preserve information and achieve nearly zero power dissipation as operating frequencies approach zero. Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. Although their origins can be traced back to the early adiabatic circuits, these socalled energyrecovering systems approach charge recycling from a more practical angle, achieving operating frequencies in the hundreds of MHz with relatively low overhead. Among other energy recovering designs, researchers in the field have demonstrated microcontrollers, standardcell ASICs, SRAMs, LCD panel drivers, I/O drivers, and multiGHz clock networks. In this tutorial, we will present an overview of the field, focusing on the most promising charge recovering design techniques for ASICs that are close to integration into the field. I.
Comparison of high speed voltagescaled conventional and adiabatic circuits
 ISLPED Intern. Symposium on Low Power Electronics and Design
, 1996
"... The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energyrecovering logic families. Using a circuit simulator, the supplies and operating voltages of each family are optimized for minimum power consumption at ..."
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The power versus frequency performance of a micropipelined conventional CMOS logic family is compared with that of three similarly pipelined energyrecovering logic families. Using a circuit simulator, the supplies and operating voltages of each family are optimized for minimum power consumption at each frequency. One of the energyrecovering logic families is shown to be capable of substantially lower dissipation than the conventional case, one is comparable, and one is worse.
Pipelined DSP Design with a True SinglePhase EnergyRecovering Logic Style
 In: Proc. I.E.E.E. Alessandro Volta Memorial Workshop on Low Power Design
, 1999
"... We recently invented a true singlephase energyrecovering circuit family, called TSEL, that relies on a crosscoupled latch structure and two DC reference voltages to achieve low energy consumption for a broad range of operating frequencies. In this paper, we explore the application of TSEL to the ..."
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We recently invented a true singlephase energyrecovering circuit family, called TSEL, that relies on a crosscoupled latch structure and two DC reference voltages to achieve low energy consumption for a broad range of operating frequencies. In this paper, we explore the application of TSEL to the design of lowenergy DSP circuits. Specically, we describe and evaluate a 6,768transistor, pipelined TSEL module that performs the 8point Hadamard Transform. In layout simulations with a standard 0.5m CMOS technology, our TSEL module functions correctly for operating frequencies in excess of 280MHz. Above 40MHz, our TSEL design is more energyecient than any other energyrecovering alternative with a similar crosscoupled latch structure. At 280MHz, it is at least 4 times more energyecient than a corresponding static CMOS design. 1: Introduction Energy recovery is a promising approach to the design of extremely low energy VLSI circuits [1, 2, 3, 5, 10]. Energyrecovering (a.k.a. adiab...
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor
 Sizing, Proceedings of the 13th International Workshop on Power And Timing Modeling, Optimization and Simulation, PATMOS’03
, 2003
"... Abstract. Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations ..."
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Abstract. Positive Feedback Adiabatic Logic (PFAL) with minimal dimensioned transistors can save energy compared to static CMOS up to an operating frequency f = 200MHz. In this work the impact of transistor sizing is discussed, and design rules are analytically derived and confirmed by simulations. The increase of the pchannel transistor width can significantly reduce the resistance of the charging path decreasing the energy dissipation of the PFAL inverter by a factor of 2. In more complex gates a further design rule for the sizing of the nchannel transistors is proposed. Simulations of a PFAL 1bit full adder show that the energy consumption can be reduced by additional 10 % and energy savings can be achieved beyond f = 1GHz in a 0.13µm CMOS technology. The results are validated through the use of the design centering tool ‘WiCkeD ’ [1]. 1