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A Study of Injection Locking and Pulling in Oscillators
, 2004
"... Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase nois ..."
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Cited by 14 (0 self)
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Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phaselocked oscillators under injection pulling is also formulated.
Design and optimization of LC oscillators
, 1999
"... We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, ..."
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Cited by 7 (2 self)
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We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal tradeoff curves between competing objectives such as phase noise and power.
122 A 2.6GHzE.2GHz Frequency Synthesizer in 0.4pm CMOS Technology
"... at both the architecture and the circuit level. The high center This paper describes the design of CMOS a frequency synfrequency of the voltagecontrolled oscillator (VCO), the poor thesizer targeting wireless local area network applications quality of inductors due to skin effect and substrate loss ..."
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at both the architecture and the circuit level. The high center This paper describes the design of CMOS a frequency synfrequency of the voltagecontrolled oscillator (VCO), the poor thesizer targeting wireless local area network applications quality of inductors due to skin effect and substrate loss, the in the 5GHz range. Based on an integerN architecture, limited tuning range, the nonlinearity of the VCO inputloutput the synthesizer produces a 5.2GHz output as well as the characteristic, the high speed required of the dualmodulus quadrature phases of a 2.6GHz carrier. Fabricated in a divider, the mismatches in the charge pump, and the imple0.4pm digital CMOS technology, the circuit provides a mentation of the loop filter are among the issues encountered channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of115 dBdHz at 2.6 GHz and100 dBdHz in this design. In order to relax some of the synthesizer requirements, the at 5.2 GHz at 10MHz offset. The reference sidebands are transceiver and the synthesizer have been designed concurat50 dBc at 2.6 GHz and the power dissipation from a rently. Fig. 1 shows the transceiver architecture [2] and 2.6V supply is 47 mW. I.
A 900MHz CMOS Bandpass Amplifier for Wireless Receivers
, 1999
"... This dissertation describes the design of a CMOS 900MHz bandpass amplifier that is suitable for RF transceivers. The work employs the stateofart inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input ..."
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This dissertation describes the design of a CMOS 900MHz bandpass amplifier that is suitable for RF transceivers. The work employs the stateofart inductive degeneration techniques to minimize the noise figure and explores the use of lossy spiral inductors in high frequency circuit to realize input matching networks onchip. A Qcompensation circuit is included to achieve a 25MHz 3dB bandwidth. Besides, a center frequency tuning circuit is also embedded to compensate for frequency deviations due to process variations. In the first prototype, a secondorder bandpass amplifier had been fabricated in standard 0.8 μm singlepoly, triplemetal CMOS process (HP SCN26G) provided by MOSIS ®. With a 3V supply, at 950MHz and a 3dB bandwidth of 25MHz, the measured voltage gain is 26 dB and the input S 11 is13 dB. Under the same baising condition, the input thirdorder intermodulation product (IIP 3) and inputreferred 1dB compression point (P o,1dB) are 21.5 dBm and31.5 dBm respectively. The image rejection at 140MHz away from the desired signal is 20 dB. In addition, the Q of the amplifier can be tuned from around 2 to infinity and the center frequency can also be varied from 930 MHz to 1040 MHz. On the grounds that the measured
5.2GHz CMOS HIPERLAN Transceivers
"... This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5GHz range, with emphasis on the HIPERLAN standard. Based on an integerN architecture, the synthesizer produces a 5.2GHz output as well as the quadrature phases of a 2.6GHz c ..."
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This paper describes the design of a CMOS frequency synthesizer targeting wireless local area network applications in the 5GHz range, with emphasis on the HIPERLAN standard. Based on an integerN architecture, the synthesizer produces a 5.2GHz output as well as the quadrature phases of a 2.6GHz carrier. Fabricated in a 0.4 m digital CMOS technology, the circuit provides a channel spacing of 23 MHz at 5.2 GHz while exhibiting a phase noise of,115 dBc/Hz at 2.6 GHz and,100 dBc/Hz at 5.2 GHz at 10MHz offset. The reference sidebands are at,50 dBc at 2.6 GHz and the power dissipation from a 2.6V supply is 47 mW. I.