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The Semantic Challenge of Verilog HDL
 IN TENTH ANNUAL IEEE SYMPOSIUM ON LOGIC IN COMPUTER SCIENCE, IEEE COMPUTER
, 1995
"... The Verilog hardware description language (HDL) is widely used to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the propagation of changes. Different Verilog models of the ..."
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Cited by 34 (1 self)
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The Verilog hardware description language (HDL) is widely used to model the structure and behaviour of digital systems ranging from simple hardware building blocks to complete systems. Its semantics is based on the scheduling of events and the propagation of changes. Different Verilog models of the same device are used during the design process and it is important that these be `equivalent'; formal methods for ensuring this could be commercially significant. Unfortunately, there is very little theory available to help. This selfcontained tutorial paper explains the semantics of Verilog informally and poses a number of logical and semantic problems that are intended to provoke further research. Any theory developed to support Verilog is likely to be useful for the analysis of the similar (but more complex) language VHDL.
Formal Reasoning with Verilog HDL
 In Workshop on Formal Techniques for Hardware and Hardwarelike Systems, Marstrand
, 1998
"... Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis ..."
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Cited by 8 (2 self)
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Most hardware verification techniques tend to fall under one of two broad, yet separate caps: simulation or formal verification. This paper briefly presents a framework in which formal verification plays a crucial role within the standard approach currently used by the hardware industry. As a basis for this, the formal semantics of Verilog HDL are defined, and properties about synchronization and mutual exclusion algorithms are proved.
A Theory of combinational programs
 in the proceedings of the Asian Paci Software Engineering Conference, APSEC
, 1999
"... The actual behaviour of a hardware devices available for an implementation of a control system can be simulated by a program, and this allows a hardware device to be proved correct by standard software techniques. This report takes advantage of algebraic approaches in investigation of simulator algo ..."
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Cited by 6 (0 self)
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The actual behaviour of a hardware devices available for an implementation of a control system can be simulated by a program, and this allows a hardware device to be proved correct by standard software techniques. This report takes advantage of algebraic approaches in investigation of simulator algorithm. Here we formalise Event semantics of Hardware Description Language in the form of relations and use Relation calculus to prove properties of combinational programs, cycle behaviours of which are defined as a conditional loop of nondeterministic choices between generalised parallel assignments. This reports investigates the properties (including termination and stability and uniqueness of final state) of combinational programs, and explores the condition under which a combination program can be reduced to a sequential normal form by removing all the parallel operators. We examine three classes of programs which are widely used in design of wellbehaved combinational circuits. Tran V...
Hardware Design Based on Verilog HDL
, 1998
"... Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to ..."
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Cited by 4 (2 self)
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Up to a few years ago, the approaches taken to check whether a hardware component works as expected could be classified under one of two styles: hardware engineers in the industry would tend to exclusively use simulation to (empirically) test their circuits, whereas computer scientists would tend to advocate an approach based almost exclusively on formal verification. This thesis proposes a unified approach to hardware design in which both simulation and formal verification can coexist. Relational Duration Calculus (an extension of Duration Calculus) is developed and used to define the formal semantics of Verilog HDL (a standard industry hardware description language). Relational Duration Calculus is a temporal logic which can deal with certain issues raised by the behaviour of typical hardware description languages and which are hard to describe in a pure temporal logic. These semantics are then used to unify the simulation of Verilog programs, formal verification and the use of algebraic laws during the design stage.
Semantics of a VerificationOriented Subset of VHDL
 In CHARME'95, volume 987 of Lecture Notes in Computer Science
, 1995
"... . This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machi ..."
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Cited by 4 (1 self)
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. This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machines for its embedded processes and blocks. The kernel process in our model is distributed among the composed machines. One transition of the final abstract machine models a VHDL delta cycle. This model can be used for symbolic model checking and equivalence verification. 1 Introduction Giving a formal definition of the semantics of VHDL [7] is of highest importance for synthesis and formal verification. Many different approaches have been proposed to fulfill this need, see eg [1, 3, 4, 5, 8, 9, 10, 11]. A first conclusion can be drawn from a study of these works: one has to trade off the number of VHDL features modeled, and the practical usefulness of the semantics. VHDL is a very complex l...
A Model of VHDL for the Analysis, Transformation, and Optimization of Digital System Designs
 In Conference on Hardware Description Languages (CHDL '95
, 1995
"... Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses wellformedness, static equivalences, and static r ..."
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Cited by 3 (2 self)
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Besides a formal syntax definition, few formal semantic models for HDLs are ever constructed. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL that addresses wellformedness, static equivalences, and static rewriting is presented. A rewriting algebra is presented that defines a set of transforms that allow the rewriting of VHDL descriptions into a reduced form. The dynamic semantics is under development and the reductions attained by the rewriting algebra have greatly simplified the language constructs that the dynamic semantics have to characterize. I. Introduction Hardware Description Languages (HDLs) and their affiliated design tools are widely used to aid the computer architect in the design and implementation of digital systems. In many cases such languages and tools are proprietary systems  used locally at only one or two sites. However, advances in design automation have driven the co...
Approaching the Denotational Semantics of Behavioral VHDL Descriptions
, 1993
"... In this paper, we present a framework for defining the formal semantics of behavioral VHDL92 descriptions. We propose a complementary application of denotational and operational semantics. The static semantics is defined by denotational means. The definition of the dynamic semantics is based on an o ..."
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In this paper, we present a framework for defining the formal semantics of behavioral VHDL92 descriptions. We propose a complementary application of denotational and operational semantics. The static semantics is defined by denotational means. The definition of the dynamic semantics is based on an operational model using Interval Event Structures. 1 Introduction Approaching the definition of a formal semantics of the IEEE Std1076 hardware description language VHDL [VHDL87] as well as of its successor VHDL92 [VHDL92] is of high interest for the synthesis and the formal verification of VHDL designs. First work in the formal definition of VHDL87 has been done by Borrione and Paillet [BoPa87] defining the formal semantics of a VHDL subset in terms of a functional model. Wilsey [Wilsey90] defines the semantics of a small VHDL87 subset based on interval temporal logic. More recently Davis [Davis93] has introduced the denotational semantics of the VHDL87 simulation cycle by the use of an in...
A Model for the Dynamic Semantics of VHDL for CAD Tool Optimization
, 1995
"... Present day hardware complexity mandates prior simulation of designs to achieve some level of confidence about their correctness. The hardware description language VHDL is widely used to describe and simulate hardware designs. However, the semantics of VHDL, presented in informal prose form in the L ..."
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Present day hardware complexity mandates prior simulation of designs to achieve some level of confidence about their correctness. The hardware description language VHDL is widely used to describe and simulate hardware designs. However, the semantics of VHDL, presented in informal prose form in the Language Reference Manual (LRM), is ambiguous and therefore needs to be formalized. Past efforts in characterizing VHDL are lacking in either that they handle only a small subset of VHDL or that they simply describe the simulation cycle as prescribed by the LRM (usually both). In this work, a comprehensive, declarative semantics for VHDL is presented which is independent of the simulation cycle and uses a temporal logic that captures the timing constraints crucial to the understanding of a discrete event based language like VHDL. The semantics is presented as a construction of sets of time intervals over which the values of signals, ports and variables are defined. It is argued that this sema...