research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There is a second research laboratory located in Palo Alto, the Systems Research Center (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge,

research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There are two other research laboratories located in Palo Alto, the Network Systems

Routing Architecture and Layout Synthesis for Multi-FPGA Systems Doctor of Philosophy, 1999 Mohammed A. S. Khalid Department of Electrical and Computer Engineering University of Toronto Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected.

We describe a technique for estimating the floating body potentials of partially-depleted silicon-on-insulator (PD-SOI) circuits under steady switching activity and under initial activity after a long period of quiescence. The approach is based on a unique state diagram abstraction of the PD-SOI FET that captures all of the essential device physics. This picture yields a simple analytic model of the body voltage which is used within the context of a prototype transistorlevel static timing analysis engine. Results are presented that demonstrate the accuracy of the analytic body-voltage model and the reduction in delay uncertainty possible with this technique. 1 Introduction Silicon-on-insulator (SOI) technology has long found niche applications for radiation-hardened or high-voltage integrated circuits. Recently, SOI has emerged as a technology for highperformance, low-power deep-submicron digital integrated circuits [1, 2]. For digital applications, fully-depleted devices have been ...

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96] [Babb97] and previous research has shown that the partial crossbar is one of the best existing architectures [Kim96] [Khal97]. In this paper we propose a new routing architecture, called the Hybrid Complete-Graph and Partial-Crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hardwired and programmable connections between the FPGAs. We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and inter-chip routing tools were developed, with particular attention paid to architecture-appropriate inter-chip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20 % more than the new HCGP architecture and as much as 25 % more. Furthermore, the critical path delay for designs implemented on the partial crossbar were on average 20 % more than the HCGP architecture and up to 43% more. Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture: the proportion of hard-wired connections versus programmable connections, to determine its best value. 1

Existing static timing analyzers make several assumptions about circuits, implicitly trading off accuracy for speed. In this paper we examine the validity of these assumptions, notably the slope approximation to waveforms, single-input transitions, and the choice of a propagating signal based on a single voltage-time point. We provide data on static CMOS gates that show delays obtained in this way can be optimistic by more than 30%. We propose a new approach, Waveform-based Timing Analysis that employs a state-ofthe-art circuit simulator as the underlying delay modeler. We show that such an approach can achieve more accurate delays than slope-based timing analyzers at a computation cost that still allows iterations between design modification and delay analysis. 1.

Although the trend toward finer geometries and larger chips has produced faster systems, it has also created larger voltage drops and higher current densities in chip power supply networks. Excessive voltage drops in the power supply lines cause incorrect circuit operation, and high current densities lead to circuit failure via electromigration. Analyzing this power supply noise by hand for large circuits is difficult and error prone; automatic checking tools are needed to make the analysis easier. This thesis describes Ariel, a CAD tool that helps VLSI designers analyze power supply noise. The system consists of three main components, a resistance extractor, a current estimator, and a linear solver, that are used together to determine the voltage drops and current density along the supply lines. The resistance extractor includes two parts: a fast extractor that calculates resistances quickly using simple heuristics, and a slower, more accurate finite element extractor. Despite its simplicity, the fast extractor obtained nearly the same results as the finite element one and is two orders of magnitude faster. The system also contains two current estimators, one for CMOS

Abstract — A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits. I.

The design of a 1 ns cycle-time microprocessor by a small team poses unique problems in computer-aided design. In this paper, we describe a complete set of tools which combines the obsession with performance of full custom design with the ease of use of semi-custom design. d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA Table of Contents 1. Introduction 1 2. Design Capture 2 3. Interface to Simulators 3 4. Generation of Layout 4 5. Conclusion 7 6. Acknowledgements 7 References 8 1. Introduction Researchers at Digital Equipment Corporation's Western Research Laboratory are currently designing BIPS-1, a single-chip ECL microprocessor with a 1 nanosecond cycle time. Using a sub-micron BICMOS technology, this processor will be about 15mm on a side and will contain 4 million active devices. A major part of this project is the design of a comprehensive set of computer-aided design tools. Early in the project we quickly determined that a...

Abstract—Convex-optimization techniques are very popular in the very large-scale-integration design society due to their guaranteed convergence to a global optimal point. The table data need to be fitted into convex forms to be used in the convex optimization problems. Fitting the tables into posynomials, which are analytically convex under logarithmic transformation, may suffer from the excessive fitting errors as the fitting problem is nonconvex. In this paper, we propose to directly adjust the lookup-table values into a numerically convex lookup table without any explicit analytical form. We show that numerically “convexifying ” the lookup-table data with minimum perturbation can be formulated as a convex semidefinite optimization problem, and hence, optimality can be reached in polynomial time. We also propose three algorithms to make the table data smooth to enable faster convergence of the convex optimizer. Results from extensive experiments on industrial cell libraries demonstrate 9.6 × improvement in fitting error over a welldeveloped posynomial-fitting procedure. We illustrate the effectiveness of this model in a convex optimization problem by providing results for using our model in the optimal gate sizing of standard cells. We observe a 5.07 % improvement in the delay of International Symposium on Circuits and Systems (ISCAS) benchmark circuits over the posynomial-fitting procedure. Index Terms—Convex optimization, gate sizing, semidefinite programming. I.