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Optimal Wire and Transistor Sizing for Circuits with NonTree Topology
, 1997
"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."
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Cited by 29 (11 self)
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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interiorpoint methods for semidefinite programming. The method is applied to two important sizing problems sizing of clock meshes, and sizing of buses in the presence of crosstalk.
Optimizing dominant time constant in RC circuits
, 1996
"... We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interestin ..."
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Cited by 15 (7 self)
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We propose to use the dominant time constant of a resistorcapacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with nongrounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.
A gatedelay model for highspeed CMOS circuits
 Proc. 31st ACM/IEEE Design Automation Conference
, 1994
"... Abstract As signal speeds increase and gate delays decrease for highperformance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gateoutput impedances make it more difficult to empiri ..."
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Cited by 13 (3 self)
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Abstract As signal speeds increase and gate delays decrease for highperformance digital integrated circuits, the gate delay modeling problem becomes increasingly more difficult. With scaling, increasing interconnect resistances and decreasing gateoutput impedances make it more difficult to empirically characterize gatedelay models. Moreover, the singleinputswitching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today’s highspeed logic paths. In this paper a new empirical gate delay model is proposed. Instead of building the empirical equations in terms of capacitance loading and inputsignal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived kfactor models and switchresistor models to efficiently: 1) handle capacitance shielding due to metal interconnect resistance, 2) model the RC interconnect delay, and 3) provide tighter bounds for simultaneous switching. I.
Moment Models of General Transmission Lines with Application to Interconnect Analysis and Optimization
 Proc. IEEE MultiChip Module Conf
, 1995
"... In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the v ..."
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Cited by 6 (1 self)
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In this paper, we present new moment models for uniform, nonuniform and coupled transmission lines. The moment model of a line is based on the relationships between the two port currents (KCL) and the two port voltages (KVL) of the line. The parameters of the model depend on the mean values of the voltage moments and the weighted voltage moments of the line. Simple formulas are given to compute these mean values efficiently. By using such models and moment matching techniques, interconnects modeled as transmission line networks can be efficiently simulated. In addition, by using moment sensitivities, we demonstrate that wire sizing optimization can be carried out for layout design. 1 Introduction With the rapid increase of the signal frequency and decrease of the feature sizes in high speed electronic circuits, interconnects play increasingly important roles. Not only the signal delay due to interconnects is often significantly larger than the transistor delay, On leave from Nanjin...
Application of Negative Group Delay Active Circuits to Reduce the 50
 Propagation Delay of RCLine Model,” 12th IEEE Workshop on SPI
, 2008
"... This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RCtransmission line model. The synthesis method of NGD circuits versus th ..."
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Cited by 2 (2 self)
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This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RCtransmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2cmlong RCline model, timedomain simulations carried out with a highfrequency circuit simulator showed that the 50 % propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, onchip, longline, …) are discussed. In highspeed applications, time delay has become a major
A Performance Analysis Tool For PerfomanceDriven MimCell Generatiom
"... A new method ispresented to determine thepower dissipation and propagationdelay time of small logical blocks (microcells). This method is a combination of the RCtree and the macro modeling methodr. It is a fast and accurate method, three orden of magnitude faster that SPICE, while the maximal err ..."
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A new method ispresented to determine thepower dissipation and propagationdelay time of small logical blocks (microcells). This method is a combination of the RCtree and the macro modeling methodr. It is a fast and accurate method, three orden of magnitude faster that SPICE, while the maximal error is 10 percent. This method will be used in a performancedriven microcell generator for a seaofgates environment. 1.
A New and Accurate Interconnection Delay Time Evaluation in a general Tree–Type Network.
"... In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results, would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed ..."
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In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results, would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification. 1.
Approved by: FAST INTERCONNECT OPTIMIZATION
, 2005
"... As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multimillion ..."
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As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multimillion gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on nontree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log 2 n) optimal algorithm that runs much faster than the previous classical van Ginneken’s O(n 2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn 2)time