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Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
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We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
Formal Verification of a Theory of IEEE Rounding
 TPHOLs 2001: Supplemental Proceedings, Informatics Research Report EDIINFRR0046
, 2001
"... We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round dec ..."
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Cited by 6 (1 self)
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We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round decomposition are formalized, allowing for a subdivision of floating point units into smaller building blocks, which then can be verified separately. The theory has been successfully applied to the verification of a fully IEEE compliant floating point unit.
Formal verification of the VAMP microprocessor (project status
 In Witold Charatonik and Harald Ganzinger, editors, Symposium on the Effectiveness of Logic in Computer Science (ELICS02
, 2002
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