Results 1 
6 of
6
Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
Abstract

Cited by 17 (6 self)
 Add to MetaCart
(Show Context)
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
Formal Verification of a Theory of IEEE Rounding
 TPHOLs 2001: Supplemental Proceedings, Informatics Research Report EDIINFRR0046
, 2001
"... We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round dec ..."
Abstract

Cited by 6 (1 self)
 Add to MetaCart
We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round decomposition are formalized, allowing for a subdivision of floating point units into smaller building blocks, which then can be verified separately. The theory has been successfully applied to the verification of a fully IEEE compliant floating point unit.
Numerical Replication of Computer Simulations: Some Pitfalls and How To Avoid Them
, 2000
"... A computer simulation, such as a genetic algorithm, that uses IEEE standard oatingpoint arithmetic may not produce exactly the same results in two dierent runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the result ..."
Abstract

Cited by 6 (0 self)
 Add to MetaCart
(Show Context)
A computer simulation, such as a genetic algorithm, that uses IEEE standard oatingpoint arithmetic may not produce exactly the same results in two dierent runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the results from one run replicate those from another but should verify this by actually comparing the data. However, researchers who are aware of this pitfall can reliably replicate simulations, in practice. This paper discusses the problem and suggests solutions.
Formalizing Java's Two'sComplement Integral Type in Isabelle/HOL
 In Eighth International Workshop on Formal Methods for Industrial Critical Systems (FMICS’03). ENTCS 80
, 2003
"... We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are p ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
(Show Context)
We present a formal model of the Java two'scomplement integral arithmetics. The model directly formalizes the arithmetic operations as given in the Java Language Specification (JLS). The algebraic properties of these definitions are derived. Underspecifications and ambiguities in the JLS are pointed out and clarified. The theory is formally analyzed in Isabelle/HOL, that is, machinechecked proofs for the ring properties and divisor/remainder theorems etc. are provided. This work is suited to build the framework for machinesupported reasoning over arithmetic formulae in the context of Java sourcecode verification.
Numerical Replication of Computer Simulations: Some Pitfalls and How To Avoid Them ∗
"... A computer simulation, such as a genetic algorithm, that uses IEEE standard floatingpoint arithmetic may not produce exactly the same results in two different runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the re ..."
Abstract
 Add to MetaCart
(Show Context)
A computer simulation, such as a genetic algorithm, that uses IEEE standard floatingpoint arithmetic may not produce exactly the same results in two different runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the results from one run replicate those from another but should verify this by actually comparing the data. However, researchers who are aware of this pitfall can reliably replicate simulations, in practice. This paper discusses the problem and suggests solutions. 1
Numerical Replication of Computer Simulations: Some Pitfalls and How To Avoid Them ∗
, 2000
"... A computer simulation, such as a genetic algorithm, that uses IEEE standard floatingpoint arithmetic may not produce exactly the same results in two different runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the re ..."
Abstract
 Add to MetaCart
(Show Context)
A computer simulation, such as a genetic algorithm, that uses IEEE standard floatingpoint arithmetic may not produce exactly the same results in two different runs, even if it is rerun on the same computer with the same input and random number seeds. Researchers should not simply assume that the results from one run replicate those from another but should verify this by actually comparing the data. However, researchers who are aware of this pitfall can reliably replicate simulations, in practice. This paper discusses the problem and suggests solutions. 1