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Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
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We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
Automatic formal verification of fusedmultiplyadd FPUs
 in DATE
, 2005
"... In this paper we describe a fullyautomated methodology for formal verification of fusedmultiplyadd floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor’s architectural specification, which may include all aspects o ..."
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In this paper we describe a fullyautomated methodology for formal verification of fusedmultiplyadd floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor’s architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD and SATbased symbolic simulation. To make this verification task tractable, we use a combination of casesplitting, multiplier isolation, and automatic model reduction techniques. The casesplitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. The methodology is directly applicable to multiGHz industrial implementation models (e.g., HDL or gatelevel circuit representations) that contain all details of the highperformance transistorlevel model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach. 1
Formal Verification of a Theory of IEEE Rounding
 TPHOLs 2001: Supplemental Proceedings, Informatics Research Report EDIINFRR0046
, 2001
"... We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round dec ..."
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Cited by 6 (1 self)
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We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round decomposition are formalized, allowing for a subdivision of floating point units into smaller building blocks, which then can be verified separately. The theory has been successfully applied to the verification of a fully IEEE compliant floating point unit.
Formal verification of the VAMP microprocessor (project status
 In Witold Charatonik and Harald Ganzinger, editors, Symposium on the Effectiveness of Logic in Computer Science (ELICS02
, 2002
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Modeling SystemC FixedPoint Arithmetic in HOL
, 2003
"... SystemC is a new Cbased system level design language whose ultimate objective is to enable SystemonaChip (SoC) design and verification. Fixedpoint design based on the SystemC data types is rapidly becoming the standard for optimizing DSP systems. In this paper, we propose to create a formalizat ..."
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SystemC is a new Cbased system level design language whose ultimate objective is to enable SystemonaChip (SoC) design and verification. Fixedpoint design based on the SystemC data types is rapidly becoming the standard for optimizing DSP systems. In this paper, we propose to create a formalization of SystemC fixedpoint arithmetic in the HOL theorem proving environment. The SystemC fixedpoint number representation which contains a new generalized format and different rounding and overflow modes is described, and then it is formalized in higherorder logic. This formalization is then compared with the formalization of IEEE standard based floatingpoint arithmetic in HOL. A set of theorems are proved to bound the error in fixedpoint rounding and to verify the fixedpoint arithmetic operations against their abstract mathematical counterparts. Finally, we show by an example how this formalization can be used in verification of the translation from floatingpoint and fixedpoint algorithmic, down to register transfer and netlist gate levels in the design flow of SoC systems.
Improved Symoblic Simulation By Dynamic Funtional Space Partitioning
"... In this paper, we provide a flexible and automatic method to partition the functional space for efficient symbolic simulation. We utilize a 2tuple list representation as the basis for partitioning the functional space. The partitioning is carried out dynamically during the symbolic simulation bas ..."
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In this paper, we provide a flexible and automatic method to partition the functional space for efficient symbolic simulation. We utilize a 2tuple list representation as the basis for partitioning the functional space. The partitioning is carried out dynamically during the symbolic simulation based on the sizes of OBDDs. We develop heuristics for choosing the optimal partitioning points. These heuristics intend to balance the tradeoff between the time and space complexity. We demonstrate the effectiveness of our new symbolic simulation approach through experiments based on a floating point adder and a memory management unit. 1.
Formalization of FixedPoint Arithmetic in HOL
"... Abstract. This paper addresses the formalization in higherorder logic of fixedpoint arithmetic. We encoded the fixedpoint number system and specified the different quantization modes in fixedpoint arithmetic such as the directed and even quantization modes. We also considered the formalization o ..."
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Abstract. This paper addresses the formalization in higherorder logic of fixedpoint arithmetic. We encoded the fixedpoint number system and specified the different quantization modes in fixedpoint arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floatingpoint to fixedpoint algorithmic level in the signal processing design flow.
Improved Symbolic Simulation By FunctionalSpace Decomposition
"... Abstract — This paper presents a functionalspace decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapath of a circuit is separated, and their simulated results are recorded in different domains. A 2tuple list structure is us ..."
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Abstract — This paper presents a functionalspace decomposition approach to enhance the capability of symbolic simulation. In our symbolic simulator, the control part and datapath of a circuit is separated, and their simulated results are recorded in different domains. A 2tuple list structure is used to separate the results in the control and datapath domains. Then, the functional subspace in the control domain can further be decomposed in order to achieve the optimal OBDD size and run time. We demonstrate the effectiveness of our decomposition approach based on symbolic simulation of arithmetic circuit units. I.