This paper examines the implementation of Finite Field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2 ) with m8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the Finite Field operations by adding just a small overhead of logic. We develop division and exponentiation based on multiplication on the algorithm level and present a simple scheme for implementation of all operations on a processor datapath.

Interest in normal bases over finite fields stems both from mathematical theory and practical applications. There has been a lot of literature dealing with various properties of normal bases (for finite fields and for Galois extension of arbitrary fields). The advantage of using normal bases to represent finite fields was noted by Hensel in 1888. With the introduction of optimal normal bases, large finite fields, that can be used in secure and e#cient implementation of several cryptosystems, have recently been realized in hardware. The present thesis studies various theoretical and practical aspects of normal bases in finite fields. We first give some characterizations of normal bases. Then by using linear algebra, we prove that F q n has a basis over F q such that any element in F q represented in this basis generates a normal basis if and only if some groups of coordinates are not simultaneously zero. We show how to construct an irreducible polynomial of degree 2 n with linearly i...

University ofWaterloo

A new parallel-in-parallel-out bit-level pipelined multiplier is presented to perform multiplication in GF(2 m ). The existing designs use m 2 identical cells each having 7 latches and have a system latency of 3m. We start with the Dependence Graph (DG) of the algorithm and pipleine it to achieve a critical path equal to the delay of a 2-input AND and XOR gate. The critical path in the proposed design is the same as in previous designs. The number of latches required per cell has however, been reduced from 7 to 3. This results in considerable hardware savings and the system latency is also reduced form the present 3m to m+1 in the proposed design. A chip has been designed using Magic to implement the proposed multiplier. Introduction In recent years, Finite Fields have received a lot of attention because of their application in error control coding [1] [2]. They have also been used in digital signal processing, pseudorandom number generation, encryption and decryption protocols in...

This paper presents a new multiplication algorithm and, based on this algorithm, proposes a hardware architecture, called Modified Inner-Product Multiplier (MIPM), which computes AB multiplication based on a Linear Feedback Shift Register (LFSR)

Gröbner basis are a powerful tool with many applications in symbolic computation. In this article, we propose a linear systolic array which can be used as co-processor for efficient computation of Gröbner basis, especially dedicated for the domain of error-correcting codes. The design was made from a high level specification in the Alpha language, which provides many static analysis checks. A case study show how much time can be gain with such a co-processor.