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73
Petri Nets
 ACM Computing Surveys
, 1977
"... Over the last decade, the Petri net has gamed increased usage and acceptance as a basic model of systems of asynchronous concurrent computation. This paper surveys the basic concepts and uses of Petm nets. The structure of Petri nets, their markings and execution, several examples of Petm net models ..."
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Cited by 173 (0 self)
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Over the last decade, the Petri net has gamed increased usage and acceptance as a basic model of systems of asynchronous concurrent computation. This paper surveys the basic concepts and uses of Petm nets. The structure of Petri nets, their markings and execution, several examples of Petm net models of computer hardware and software, and
Design of Embedded Systems: Formal Models, Validation, and Synthesis
 PROCEEDINGS OF THE IEEE
, 1999
"... This paper addresses the design of reactive realtime embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the ..."
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Cited by 106 (9 self)
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This paper addresses the design of reactive realtime embedded systems. Such systems are often heterogeneous in implementation technologies and design styles, for example by combining hardware ASICs with embedded software. The concurrent design process for such embedded systems involves solving the specification, validation, and synthesis problems. We review the variety of approaches to these problems that have been taken.
Decidability Issues for Petri Nets  a survey
, 1994
"... : We survey 25 years of research on decidability issues for Petri nets. We collect results on the decidability of important properties, equivalence notions, and temporal logics. 1. Introduction Petri nets are one of the most popular formal models for the representation and analysis of parallel proc ..."
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Cited by 89 (5 self)
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: We survey 25 years of research on decidability issues for Petri nets. We collect results on the decidability of important properties, equivalence notions, and temporal logics. 1. Introduction Petri nets are one of the most popular formal models for the representation and analysis of parallel processes. They are due to C.A. Petri, who introduced them in his doctoral dissertation in 1962. Some years later, and independently from Petri's work, Karp and Miller introduced vector addition systems [47], a simple mathematical structure which they used to analyse the properties of "parallel program schemata', a model for parallel computation. In their seminal paper on parallel program schemata, Karp and Miller studied some decidability issues for vector addition systems, and the topic continued to be investigated by other researchers. When Petri's ideas reached the States around 1970, it was observed that Petri nets and vector addition systems were mathematically equivalent, even though thei...
Decidability and complexity of Petri net problems  an Introduction
 In Lectures on Petri Nets I: Basic Models
, 1998
"... . A collection of 10 "rules of thumb" is presented that helps to determine the decidability and complexity of a large number of Petri net problems. 1 ..."
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Cited by 83 (2 self)
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. A collection of 10 "rules of thumb" is presented that helps to determine the decidability and complexity of a large number of Petri net problems. 1
An introduction to asynchronous circuit design
 THE ENCYCLOPEDIA OF COMPUTER SCIENCE AND TECHNOLOGY
, 1997
"... ..."
FunState  An Internal Design Representation for Codesign
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2001
"... In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevan ..."
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Cited by 46 (11 self)
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In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models such as Boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets can be represented in the FunState model of computation. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph. The feasibility of the novel approach is shown with an ATM switch example.
Complexity Results for 1safe Nets
, 1993
"... We study the complexity of several standard problems for 1safe Petri nets and some of its subclasses. We prove that reachability, liveness, and deadlock are all PSPACEcomplete for 1safe nets. We also prove that deadlock is NPcomplete for freechoice nets and for 1safe freechoice nets. Finally, ..."
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Cited by 44 (7 self)
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We study the complexity of several standard problems for 1safe Petri nets and some of its subclasses. We prove that reachability, liveness, and deadlock are all PSPACEcomplete for 1safe nets. We also prove that deadlock is NPcomplete for freechoice nets and for 1safe freechoice nets. Finally, we prove that for arbitrary Petri nets, deadlock is equivalent to reachability and liveness. This paper is to be presented at FST&TCS 13, Foundations of Software Technology & Theoretical Computer Science, to be held 1517 December 1993, in Bombay, India. A version of the paper with most proofs omitted is to appear in the proceedings. 1 Introduction Petri nets are one of the oldest and most studied formalisms for the investigation of concurrency [33]. Shortly after the birth of complexity theory, Jones, Landweber, and Lien studied in their classical paper [24] the complexity of several fundamental problems for Place/Transition nets (called in [24] just Petri nets). Some years later, Howell,...
Phased Logic: Supporting the Synchronous Design Paradigm with DelayInsensitive Circuitry
, 1996
"... Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delayinsensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute lowskew clock signals and carefully ..."
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Cited by 34 (0 self)
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Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delayinsensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute lowskew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on LevelEncoded twophase DualRail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable...
Handshake Protocols for DeSynchronization
 IN INTERNATIONAL SYMPOSIUM ON ADVANCED RESEARCH IN ASYNCHRONOUS CIRCUITS AND SYSTEMS. 2004
, 2004
"... Desynchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for desynchronization and formally proves their correctness. A taxonomy of existing protocols for latch controllers is provided. In particul ..."
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Cited by 27 (6 self)
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Desynchronization appears as a new paradigm to automate the design of asynchronous circuits from synchronous netlists. This paper studies different protocols for desynchronization and formally proves their correctness. A taxonomy of existing protocols for latch controllers is provided. In particular, fourphase handshake protocols devised for micropipelines are studied. A new controller with maximum concurrency for desynchronization is also proposed. The applicability of desynchronization on an implementation of the DLX microprocessor is also described and discussed.