We present several fast, practical linear-complexity scheduling algorithms that enable provision of various quality-of-service (QoS) guarantees in an input-queued switch with no speedup. Specifically, our algorithms provide per-virtual-circuit transmission rate and cell delay guarantees using a credit-based bandwidth reservation scheme. Our algorithms also provide approximate max-min-fair sharing of unreserved switch capacity. The novelties of our algorithms derive from judicious choices of edge weights in a bipartite matching problem. The edge weights are certain functions of the amount and waiting times of queued cells and credits received by a virtual circuit. By using a linear-complexity variation of the well-known stable marriage matching algorithm, we present theoretical proofs and demonstrate by simulations that the edge weights are bounded. This implies various QoS guarantees or contracts about bandwidth allocations and cell delays. Network management can then provide these co...

A significant research effort has been devoted in recent years to the design of simple and efficient scheduling policies for Input Queued (IQ) and Combined Input Output Queued (CIOQ) packet switches. As a result, a number of switch control algorithms have been proposed. Among these, scheduling policies based on Maximum Weight Matching (MWM) were identified as optimal, in the sense that they were proved to achieve 100% throughput under any admissible arrival process satisfying the strong law of large number.

Abstract—We consider input-queued switch architectures dealing at their interfaces with variable-size packets, but internally operating on fixed-size cells. Packets are segmented into cells at input ports, transferred through the switching fabric, and reassembled at output ports. Cell transfers are controlled by a scheduling algorithm, which operates in packet-mode: all cells belonging to the same packet are transferred from inputs to outputs without interruption. We prove that input-queued switches using packet-mode scheduling can achieve 100 % throughput, and we show by simulation that, depending on the packet size distribution, packet-mode scheduling may provide advantages over cell-mode scheduling. Index Terms—Input queued switched, packet switching, scheduling algorithms, variable size packets. I.

The Dual Round-Robin Matching (DRRM) switch [2] [3] has a scalable, low complexity architecture which allows for an aggregate bandwidth exceeding 1 Tb/s using current CMOS technology. In this paper we prove that the DRRM switch can achieve 100% throughput under i.i.d. and uniform traffic. The DRRM is the first practical matching scheme for which this property has been proved. The performance of the DRRM switch is then studied and compared with the iSLIP switch. The delay performance under uniform traffic and the hot-spot throughput of DRRM is better than that of iSLIP, while the throughput of iSLIP under some non-uniform traffic scenarios is slightly higher than that of DRRM. Since throughput drops below 100% under nonuniform traffic, we also examine some variations of the DRRM matching scheme for nonuniform traffic. Keywords--- switching,scheduling,Virtual Output Queueing, Dual Round Robin. I.

Input-queued switch architectures play a major role in the design of high performance switches and routers for packet networks. These architectures must be controlled by a scheduling algorithm, which solves contentions in the transfer of data units from inputs to outputs. Several scheduling algorithms were proposed in the literature for input-queued cell switches, operating on fixed-size data units. In this paper we consider the case of packet switches, i.e., devices operating on variable-size data units at their interfaces, but internally operating on cells, and we propose novel extensions of known scheduling algorithms. We prove that the maximum throughput achievable by input-queued packet switches is identical to that achievable with input- and output-queued cell switches. We show by simulation that, in the case of packet switches, input-queued architectures may provide performance advantages over output-queued architectures.

Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clock frequencies increase, scaled wires become relatively slower, and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared (semi)-global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role play.

A basic problem faced by designers of high-bandwidth switches and routers is to provide effective techniques for scheduling the routing of cells through crossbars. The problem is particularly important under heavy loads or when quality-of-service (QoS) is to be supported. Much previous work on scheduling has focused on maximum bipartite matching (MBM), maximum weight bipartite matching (MWBM), and heuristics to approximate MBM and MWBM solutions. In this paper, we introduce the Shakeup technique: a randomized approach that can be used in conjunction with a number of existing heuristics to substantially improve solution quality. The Shakeup approach is conceptually simple and is supported by both theoretical and experimental results. In addition, this paper provides for the first time a framework for experimental scheduler analysis. We give extensive head-to-head comparisons of stability ranges for a number of previously proposed schedulers, and work towards the development of benchmark...

To deal with the increasing design complexity of integrated systems reuse of intellectual property (IP) blocks is promoted. A system architecture then becomes a composition of a heterogeneous set of such IP blocks together with a network that interconnects these blocks. The main challenge of system design therefore shifts from computation (IP blocks) to communication and storage (interconnect and memories). This means that applications become dynamic compositions of IP blocks which requires that the network is scalable (in the number of attached IP blocks), programmable and behaves predictably under the traffic offered by those blocks. As the feature size decreases the relative cost of wires increases. We therefore search for an interconnect network that efficiently uses wires through sharing by introducing routers. For a flexible and efficient solution at least two traffic classes must be support by the network, viz., guaranteedthroughput (GT) and best-effort (BE). For GT traffic communication channels are set up to transport data between IP blocks (possibly via memory). Best-effort traffic is never lost, but no latency or through-put guarantees are given. We also address the conflicting requirements of GT and BE traffic [1]. Our router is packet-switched and uses input-queuing with an efficient packet/flit scheduling [2] for BE traffic, whereas efficient time division multiplexing scheme is used is used for GT traffic. The focus of this paper is on the derivation of a costeffective router and network suitable for on-chip integration.

Input buffered switches have the strong advantage of efficient crossbar usage. Virtual Output Queueing (VOQ) has to be established to circumvent the head-of-line (HOL) blocking which limits the throughput to 58.6%. Arbitration algorithms control the access to the switch fabric in each time slot. Weighted algorithms achieve 100% throughput with lowest delays under all admissible traffic even under highly asymmetric load. In this paper we compare existing algorithms and propose a new algorithm for weighted matching with a delay performance close to the ideal maximum weight matching. As an important step towards implementation we emphasize the finite wordlength required for weights. This can be exploited to support priorities which is required for ATM or IPv6 switches. 1 Introduction Very high speed switches are needed for future ATM and IPv6 networks. Among the switching architectures input queued switches belong to the fastest because the access rate of crossbar and buffer memory is no...

In this paper, we propose two schemes for the load balanced Birkhoff-von Neumann switches to provide guaranteed rate services. As in [7], the first scheme is based on an Earliest Deadline First (EDF) scheduling policy. In such a scheme, we assign every packet of a guaranteed rate flow a targeted departure time that is the departure time from the corresponding work conserving link with capacity equal to the guaranteed rate. By adding a jitter control mechanism in front of the buffer at the second stage and running the EDF policy at the output buffer, we show that the end-to-end delay for every packet of a guaranteed rate flow is bounded by the sum of its targeted departure time and a constant that only depends on the number of flows and the size of the switch.