This thesis describes a new class of delay generation structures which can produce precise delays with sub-gate delay resolution. These structures are based on coupled ring oscillators which oscillate at the same frequency. One such structure, called an array oscillator, consists of a linear array of ring oscillators. A unique coupling arrangement forces the outputs of the ring oscillators to be uniformly offset in phase by a precise fraction of a buffer delay. This arrangement enables the array oscillator to achieve a delay resolution equal to a buffer delay divided by the number of rings. Another structure, called a delay line oscillator, consists of a series of delay stages, each based on a single coupled ring oscillator. These delay stages uniformly span the delay interval to which they are phase locked. Each delay stage is capable of generating a phase shift that varies over a positive and negative range. These characteristics allow the structure to precisely subdivide delays into arbitrarily small intervals.

work in this thesis would not have been possible without many people whose contributions are now acknowledged. At Analog Devices Semiconductor: Larry DeVito, Rosamaria Croughwell, and Alex Gusinov, engineers with whom it was a genuine pleasure to work; Bob Surette, for outstanding support in laboratory measurements; Tony Freitas, for considerable layout expertise; Dennis Buss, for all-important financial support; Maryanne Masterson and Frank Holden for fabrication and trim support; Bob Adams, Paul Brokaw, Barrie Gilbert, Janos Kovacs, and Chris Mangelsdorf for enlightening conversations. At Tektronix: Scott Casstevens, for providing the CSA803A for high accuracy jitter measurements; Laszlo Dobos, for his insights into jitter. At Boston University: Anton Mavretic, for his direction and support; David Perreault, Mark Horenstein, and Emile Gergin for their time and effort on the

The achievable off-chip bandwidth of digital IC's is a crucial and often limiting factor in the performance of digital systems. In intra-system interfaces where both latency and bandwidth are important, source-synchronous parallel channels have been adopted as the most effective solution. This work investigates receiver and clocking circuit design techniques for increasing the signalling rate and robustness of such channels.

Improving fabrication technology enables not only the scaling of on-chip gate speeds but also the data rate of inter-chip communication interfaces. Simple low latency offchip interfaces are limited by the maximum clock frequency that can be propagated onchip. More complex serial links break this barrier, by employing high fan-in multiplexing transmitters and high fan-out de-multiplexing receivers, thus achieving bit-times on the order of an on-chip gate-delay. As technology scales, the higher signalling rates exceed the bandwidth of the external communication media. Fortunately, the increasing integration levels also enable the use of complex modulation and coding schemes to better utilize the available signal power and bandwidth for higher data rates. However, the complexity of these schemes increases the power, area, and latency overhead of the link, thus limiting their application to bandwidth-critical and wire-limited systems. With smaller feature-sizes and higher resolution requir...

CONTENTS ACKNOWLEDGMENTS ..................................................................................... v LIST OF TABLES................................................................................................ vi LIST OF FIGURES ............................................................................................vii SUMMARY............................................................................................................. x Chapter I. INTRODUCTION .........................................................................1 Chapter II. BACKGROUND AND SYSTEM REQUIREMENT ................7 2.1 Background .....................................................................................7 2.2 System Requirements...................................................................24 Chapter III. A SCALEABLE CMOS CURRENT-MODE PREAMPLIFIER DESIGN AND INTEGRATION...............32 3.1 Introdu

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

We have designed a process-insensitive preamplifier for an optical receiver, fabricated it in several different minimum feature sizes of standard digital CMOS, and demonstrated design scaleability of this analog integrated circuit design. The same amplifier was fabricated in a 1.2 µm and two different 0.8 µm processes through the MOSIS foundry [1]. The amplifier uses a multi-stage, low-gain-per-stage approach. It has a total of 5 identical cascaded stages. Each stage is essentially a current mirror with a current gain of 3. Three of these preamplifiers have been integrated with a GaAs Metal-Semiconductor-Metal (MSM) photodetector and one with an InGaAs MSM detector by using a thin-film epilayer device separation and bonding technology [2]. This quasi-monolithic front-end of an optical receiver virtually eliminates the parasitics between the photodetector and the silicon CMOS preamplifier. We have demonstrated speed and power dissipation improvement as the minimum feature size of the transistors shrink.

We present the design of a 1 Gbit/s serial link that consumes less than 160 mW and uses less than 1.2 mm 2 of die area in a 0.35 m technology. This report will focus on several of the key circuits required for the serial link. A DLL is implemented to provide the precise multi-phase clocks required for a high-speed link. A new type of phase-frequency detector appropriate for use in DLLs is implemented. A tracking loop is implemented to recover data at the receiver which includes a 64-step, hierarchical phase interpolator with 2 ns range and 31.25 ps precision. Samplers were designed with a calculated mean-time-to-failure of 2.4\Delta10 10 years. A testchip was fabricated in a MOSIS 0.35 m HPCMOS process and experimental results are presented. Contents 1 Introduction 1 2 External Architecture 3 2.1 Applications : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 3 2.2 Unit Data Rate : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :...

to ensure proper tracking PhDet Filter Data Receiver clk0-N D IN ref Multi-phase Delay sel D OUT D 0 D 1 D 2 clk 0 clk 1 clk 2 clk 3 Data Recovery CLK PLL/DLL Hot Interconnects Tutorial Timing-5 Phase Alignment in Source Synchronous Systems . Timing information is carried by an explicit clock signal ([10]-[13]) . State can be stored either in analog filter or digital logic DLL ref ref CLK D0 D1 D2 D3 data ref CLK data CLK CLK Hot Interconnects Tutorial Timing-6 Timing Loop Performance Parameters . Phase Error: . AC - jitter: The uncertainty of the output phase . DC - phase offset: Undesired difference of the average output phase relative to the input phase. . Bandwidth: Rate at which the output phase track