Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, non-linear, non-unimodal, constrained optimization. The goal is to overcome the non-linearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others. 1 Introduction Early work on gate sizing targeting area/delay optimization can be found in [20, 12]. Using a RC delay model, TILOS [8] expresses the delay and area as posynomials. Geometric programming or heuristics based greedy approaches can be used to so...

Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives. 1. Introduction Driving buffers have been extensively used to control delays on combinatorial paths. Values of tapering factors were determined depending on the performance modeling level and on the physical representation of the cells involved with a common objective: minimizing the delay of paths. In an initial simple theory Lin and Linholm [1] introduced the fixed tapered buffer where the minimum propagation delay time is achieved when the...

We present in this paper a novel alternative for the internal power-dissipation estimation of CMOS structures. A first order macromodeling is developed, considering full submicronic additional effects such as input slew dependency of short-circuit currents and input-to-output coupling. We introduce a novel equivalent capacitance concept allowing a direct and frequencyindependent comparison of the different power components. A direct link between fanout and input/output slew is studied in order to derive design-oriented analytical macromodels for the internal power components. Validations are presented by comparing simulated values (HSPICE level 6 foundry model 0.65 m) of power components to calculated values over a wide range of inverter configurations and control conditions. Discussion is given on a first-order generalization of this macromodel to gates. Evidence is given in terms of fanout and equivalent capacitance ratio of the controlling slope contribution on the internal powerdissipation components.

This paper presents empirical models to estimate the propagation delay time and power consumed by DCFL digital circuits implemented with HFETs. Model parameters are selected performing sensitivity analysis over SPICE simulations. Sensitivity is also exploited in developing the model equations. A maximum relative error of 7% has been obtained.

This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation.

Abstract—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacitance has more significant influence on CMOS gate analysis, especially on CMOS gate static timing analysis. In this paper, the overshooting effect is modeled for CMOS inverter delay analysis in nanometer technologies. The results produced by the proposed model are close to simulation program with integrated circuit emphasis (SPICE). Moreover, the influence of the overshooting effect on CMOS inverter analysis is discussed. An analytical model is presented to calculate the CMOS inverter delay time based on the proposed overshooting effect model, which is verified to be in good agreement with SPICE results. Furthermore, the proposed model is used to improve the accuracy of the switch-resistor model for approximating the inverter output waveform. Index Terms—CMOS inverter, gate delay, nanometer technology, overshooting time, switch-resistor model, timing analysis. I.

This communication presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.

Abstract — With the scaling of CMOS technology, the overshooting time due to the input-to-output coupling capacitance has much more significant effect on inverter delay. Moreover, the overshooting time is also an important parameter in the short circuit power estimation. Therefore, in this paper an effective analytical model is proposed to estimate the overshooting time for the CMOS inverter in nanometer technologies. Furthermore, the influence of process variation on the overshooting time is illustrated based on the proposed model. And the accuracy of the proposed model is proved to greatly agree with SPICE simulation results. I.