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Model Checking via Reachability Testing for Timed Automata
, 1997
"... In this paper we develop an approach to modelchecking for timed automata via reachability testing. As our specification formalism, we consider a densetime logic with clocks. This logic may be used to express safety and bounded liveness properties of realtime systems. We show how to automatically ..."
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Cited by 48 (13 self)
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In this paper we develop an approach to modelchecking for timed automata via reachability testing. As our specification formalism, we consider a densetime logic with clocks. This logic may be used to express safety and bounded liveness properties of realtime systems. We show how to automatically synthesize, for every logical formula ', a socalled test automaton T' in such a way that checking whether a system S satisfies the property ' can be reduced to a reachability question over the system obtained by making T' interact with S.
Verification of Logic Controllers for Continuous Plants Using Timed Condition/EventSystem Models
 Automatica
, 1999
"... An approach to the formal verification of logic controllers for processes with switched continuous dynamics is presented. The method builds on modular, timed discrete event models of the plant and the controller. Subsystems with continuous dynamics are approximated algorithmically. The formal verifi ..."
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Cited by 16 (6 self)
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An approach to the formal verification of logic controllers for processes with switched continuous dynamics is presented. The method builds on modular, timed discrete event models of the plant and the controller. Subsystems with continuous dynamics are approximated algorithmically. The formal verification consists of determining the reachable discrete states of the resulting model and comparing it to a set of undesired states. For this purpose, the tool HyTech is applied. The approach is illustrated by the treatment of a process engineering example. 1 Portions of this paper were presented at the 13th IFAC World Congress, San Francisco, USA, 1996, in (Kowalewski and Preuig, 1996b) 2 Process Control Laboratory, Chemical Engineering Department, University of Dortmund, D44221 Dortmund, Germany. Corresponding author S. Kowalewski. Tel. +49 231 755 5128; Fax +49 231 755 5129; Email s.kowalewski@ct.unidortmund.de 2 1 INTRODUCTION This contribution deals with the problem of analyzing th...
Verifying Untimed and Timed Aspects of the Experimental Batch Plant
, 2001
"... We thoroughly examine the experimental batch plant in its two major operation modes: a normal operation mode and a failure operation mode. In order to do so, we use discrete condition/event system as well as timed automata for the specification and the model checking tools SMV, Kronos and HyTech ..."
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Cited by 1 (0 self)
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We thoroughly examine the experimental batch plant in its two major operation modes: a normal operation mode and a failure operation mode. In order to do so, we use discrete condition/event system as well as timed automata for the specification and the model checking tools SMV, Kronos and HyTech for verification.
Smaller Abstractions for ∀CTL∗ without Next
, 2008
"... The success of applying modelchecking to large systems depends crucially on the choice of good abstractions. In this work we present an approach for constructing abstractions when checking Nextfree universal CTL∗ properties. It is known that functional abstractions are safe and that Nextfree univ ..."
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The success of applying modelchecking to large systems depends crucially on the choice of good abstractions. In this work we present an approach for constructing abstractions when checking Nextfree universal CTL∗ properties. It is known that functional abstractions are safe and that Nextfree universal CTL∗ is insensitive to finite stuttering. We exploit these results by introducing a safe Nextfree abstraction that is typically smaller than the usual functional one while at the same time more precise, i.e., it has less spurious counterexamples.
This document in subdirectoryRS/97/29/ Model Checking via Reachability Testing for Timed Automata
, 909
"... Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS ..."
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Reproduction of all or part of this work is permitted for educational or research use on condition that this copyright notice is included in any copy. See back inner page for a list of recent BRICS Report Series publications. Copies may be obtained by contacting: BRICS
Software Verification for Embedded Systems
, 2002
"... Embedded systems have the characteristics of reactive, realtime, distributed systems. For these kind of systems formal verication is by nature complex, even more since the system interaction with its environment is often modeled, e.g., as hybrid systems. ..."
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Embedded systems have the characteristics of reactive, realtime, distributed systems. For these kind of systems formal verication is by nature complex, even more since the system interaction with its environment is often modeled, e.g., as hybrid systems.