This thesis develops an engineering practice and design methodology to enable us to use CMOS analog VLSI chips to perform more accurate and precise computation. These techniques form the basis of an approach that permits us to build computer graphics and neural network applications using analog VLSI. The nature of the design methodology focuses on defining goals for circuit behavior to be met as part of the design process. To increase the accuracy of analog computation, we develop techniques for creating compensated circuit building blocks, where compensation implies the cancellation of device variations, offsets, and nonlinearities. These compensated building blocks can be used as components in larger and more complex circuits, which can then also be compensated. To this end, we develop techniques for automatically determining appropriate parameters for circuits, using constrained optimization. We also fabricate circuits that implement multi-dimensional gradient estimation for a grad...

A non-volatile floating-gate MOSFET based trimmable current cell suitable for use in a current steering DAC and implemented in 0:35m; 3:3V CMOS technology is presented. The current source can be programmed to an accuracy corresponding to 12-bit resolution using either hot electron injection to add charge to the floating-gate or hot hole injection to remove charge. The output current from the circuit can be adjusted by 40% to overcome the relatively large variations in output current which arise when a MOSFET is biased with a low gate overdrive voltage (VgsVt) . This allows the circuit to be designed around the temperature invariant region to give an output which is temperature independent over a large trimming range. This circuit could therefore be ideally suited to operate in the uncertain thermal environment created when a DAC is incorporated within a system on chip.

A two transistor analogue circuit is described which exploits the native device characteristics of a MOSFET to calculate the square of the Euclidean distance between two points. Simulations suggest that this circuit can be employed as the basis of a lowpower vector matching architecture which could be used for vector quantisation or nearest neighbour classification. KEYWORDS floating-gate nearest-neighbour vector quantisation pattern recognition Contact author: Dr S. Collins DRA Malvern St Andrews Road Malvern Worcs WR14 3PS U.K. Tel: +44 1684 894574 Fax: +44 1684 Affiliation of authors: DRA Malvern, St Andrews Road, Malvern, Worcs WR14 3PS, UK. 1 Introduction The Euclidean distance metric is commonly used in several algorithms including nearest neighbour classification [1], vector quantisation [2] and Radial Basis Functions [3]. All these algorithms are based upon calculating the distance between an input vector and a set of reference or codebook vectors. Calculating the dist...

Control Gate Source Control Gate Drain Tunnelling Injectors Poly1 Poly2 Diffusion Implant Contact Cpp Csub Cmos -ve Injector +ve Injector Cinj Figure 1: Layout and schematic of a standard-process floating-gate MOSFET with two tunnelling injectors In order to optimise the design of the injector structures, experiments were performed upon injectors fabricated using a MOSIS-compatible 2 micron double polysilicon process. Unlike previous experiments which relied upon programming with voltage pulses, our results were obtained by employing a fixed programming voltage. The programming voltage, typically of the order of \Sigma12V , was applied to a single injector. This resulted in charge injection onto the floating-gate which causes a change in the floating-gate potential, reducing the field across the injector. The current-voltage characteristics of the charge injection mechanism can then be determined from the time-dependence of the floating-gate pot

This report is the written part of my work for the Cand.Scient degree in computer science at the Department of Informatics, University of Oslo. I thank my advisor Yngvar Berg for accepting me as one of his students, and so making this work possible, and for introducing me to the very interesting field of neural computation. I will also thank him for being encouraging, and allowing me a great freedom in choice of methods and solutions. Many thanks to Tor Sverre Lande as well, for his constructive critisism of circuit implementations. Jon-Erik Ruth

This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.